p15 (full) in projects: linux - OpenGrok search results

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Searched full:p15 (Results 1 – 25 of 210) sorted by relevance

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/linux/arch/arm/mm/
H A D	proc-mohawk.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 66 mcr p15, 0, ip, c7, c10, 4 @ drain WB 67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]`
H A D	proc-arm946.S	`48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 65 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 69 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache [all …]`
H A D	proc-arm926.S	`52 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 55 mcr p15, 0, r0, c1, c0, 0 @ disable caches 72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 73 mcr p15, 0, ip, c7, c10, 4 @ drain WB 75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 77 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 93 mrc p15, 0, r1, c1, c0, 0 @ Read control register 94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache [all …]`
H A D	proc-v7.S	`35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 38 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 89 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 120 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU 125 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB 138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 139 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 142 mrc p15, 0, r6, c3, c0, 0 @ Domain ID [all …]`
H A D	proc-v6.S	`43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 66 mcr p15, 0, r1, c7, c5, 4 @ ISB 80 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer [all …]`
H A D	proc-feroceon.S	`48 mrc p15, 0, r0, c0, c0, 1 @ read cache type register 74 mcr p15, 1, r0, c15, c9, 0 @ clean L2 75 mcr p15, 0, r0, c7, c10, 4 @ drain WB 78 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 81 mcr p15, 0, r0, c1, c0, 0 @ disable caches 98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 99 mcr p15, 0, ip, c7, c10, 4 @ drain WB 101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register [all …]`
H A D	proc-arm940.S	`41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 58 mcr p15, 0, ip, c7, c10, 4 @ drain WB 59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache [all …]`
H A D	proc-arm1020.S	`68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
H A D	proc-arm925.S	`83 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 86 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 113 mcr p15, 0, ip, c7, c10, 4 @ drain WB 115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 120 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 131 mrc p15, 0, r1, c1, c0, 0 @ Read control register 132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 134 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache [all …]`
H A D	proc-xsc3.S	57 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
H A D	proc-xscale.S	`70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 76 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 117 mrc p15, 0, r1, c1, c0, 1 119 mcr p15, 0, r1, c1, c0, 1 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches [all …]`
H A D	proc-arm920.S	`60 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 81 mcr p15, 0, ip, c7, c10, 4 @ drain WB 83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 85 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 88 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index [all …]`
H A D	proc-fa526.S	`38 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 41 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 62 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 70 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 90 mcr p15, 0, r0, c7, c10, 4 @ drain WB 108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache [all …]`
H A D	proc-sa1100.S	42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register [all …]
H A D	proc-arm922.S	`62 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 65 mcr p15, 0, r0, c1, c0, 0 @ disable caches 82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 83 mcr p15, 0, ip, c7, c10, 4 @ drain WB 85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 87 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index [all …]`
H A D	proc-arm1026.S	68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 145 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate [all …]
H A D	cache-fa.S	45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 98 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 99 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
H A D	proc-arm1022.S	`68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index [all …]`
H A D	proc-arm1020e.S	`68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
H A D	cache-v6.S	43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 143 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 150 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
H A D	proc-arm740.S	`48 mrc p15, 0, r0, c1, c0, 0 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 76 mcr p15, 0, r0, c6, c3 @ disable area 3~7 77 mcr p15, 0, r0, c6, c4 78 mcr p15, 0, r0, c6, c5 79 mcr p15, 0, r0, c6, c6 [all …]`
H A D	proc-sa110.S	38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching [all …]
H A D	cache-v4wb.S	59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 113 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 118 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 124 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 172 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
/linux/arch/arm/kernel/
H A D	hyp-stub.S	`116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) 120 mcr p15, 4, r7, c1, c1, 0 @ HCR 121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR 122 mcr p15, 4, r7, c1, c1, 3 @ HSTR 126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR 128 mrc p15, 4, r7, c1, c1, 1 @ HDCR 130 mcr p15, 4, r7, c1, c1, 1 @ HDCR 133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR 137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR 139 mrc p15, 0, r7, c0, c0, 0 @ MIDR [all …]`
/linux/arch/arm/boot/compressed/
H A D	head.S	`141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR 145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR 696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr 731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 732 mcr p15, 0, r0, c6, c7, 1 735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission [all …]`

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