Lines Matching full:p15
38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
121 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
142 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
160 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
161 mcr p15, 0, r0, c7, c10, 4 @ drain WB
169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
170 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
177 mrc p15, 0, r0, c1, c0 @ get control register v4