Lines Matching full:p15

62 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
65 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
82 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
83 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
85 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
87 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
90 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
100 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
113 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
136 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
142 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
143 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
163 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
165 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
170 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
202 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
203 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
207 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
223 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
228 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
229 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
249 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
251 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
252 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
256 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
271 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
275 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
288 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
292 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
324 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
346 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
354 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
360 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
361 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
362 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
363 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
378 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
379 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
387 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
388 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
390 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
394 	mrc	p15, 0, r0, c1, c0		@ get control register v4