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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-v3.0.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 qcom,msm-id = <246 0x30000>;
22 gpu_opp_table_3_0: opp-table-gpu30 {
23 compatible = "operating-points-v2";
25 opp-624000000 {
26 opp-hz = /bits/ 64 <624000000>;
27 opp-level = <7>;
30 opp-560000000 {
31 opp-hz = /bits/ 64 <560000000>;
32 opp-level = <6>;
[all …]
H A Dsa8540p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ &cpu0_opp_table;
10 /delete-node/ &cpu4_opp_table;
13 cpu0_opp_table: opp-table-cpu0 {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-300000000 {
18 opp-hz = /bits/ 64 <300000000>;
19 opp-peak-kBps = <(300000 * 32)>;
21 opp-403200000 {
[all …]
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. NVMEM OPP
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
[all …]
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points)
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
[all …]
H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm OPP
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
[all …]
H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic OPP (Operating Performance Points) Common Properties
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap34xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
19 clock-latency = <300000>; /* From legacy driver */
20 #cooling-cells = <2>;
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/linux/Documentation/translations/zh_CN/power/
H A Dopp.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/power/opp.rst
11 操作性能值（OPP）库
14 (C) 2009-2010 Nishanth Menon <nm@ti.com>, 德州仪器公司
20 3. OPP搜索函数
28 1.1 何为操作性能值（OPP）？
29 ------------------------------
41 {300MHz，最低电压为1V}, {800MHz，最低电压为1.2V}, {1GHz，最低电压为1.3V}
46 - {300000000, 1000000}
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/linux/arch/arm64/boot/dts/apple/
H A Ds8000.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <650>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <75000>;
[all …]
H A Ds8003.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <500>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <45000>;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson1b.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
10 cpu_opp_table: opp-table {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-44000000 {
15 opp-hz = /bits/ 64 <44000000>;
17 opp-47142000 {
18 opp-hz = /bits/ 64 <47142000>;
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dopp.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
29 * The Output Plane Processor (OPP) block groups have functions that format
31 * The key functions contained in the OPP are:
33 * - Adaptive Backlight Modulation (ABM)
34 * - Formatter (FMT) which provide pixel-by-pixel operations for format the
36 * - Output Buffer that provide pixel replication, and overlapping.
37 * - Interface between MPC and OPTC.
38 * - Clock and reset generation.
39 * - CRC generation.
56 CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
34 (opp110->regs->reg)
38 opp110->opp_shift->field_name, opp110->opp_mask->field_name
41 opp110->base.ctx
102 * 3) HW remove 12bit FMT support for DCE11 power saving reason.
115 if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) { in set_truncation()
117 if (params->flags.TRUNCATE_DEPTH == 1) in set_truncation()
122 else if (params->flags.TRUNCATE_DEPTH == 2) in set_truncation()
130 /* on other format-to do */ in set_truncation()
131 if (params->flags.TRUNCATE_ENABLED == 0) in set_truncation()
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Dqcom,rpmpd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
19 - enum:
20 - qcom,glymur-rpmhpd
21 - qcom,mdm9607-rpmpd
22 - qcom,milos-rpmhpd
23 - qcom,msm8226-rpmpd
24 - qcom,msm8909-rpmpd
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8998-bwmon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
17 - Measuring the bandwidth between CPUs and Last Level Cache Controller -
19 - Measuring the bandwidth between Last Level Cache Controller and memory
20 (DDR) - called LLCC BWMON.
25 - const: qcom,msm8998-bwmon # BWMON v4
26 - items:
[all …]
/linux/drivers/gpu/drm/amd/display/dc/opp/dcn10/
H A Ddcn10_opp.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 (oppn10->regs->reg)
36 oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
39 oppn10->base.ctx
45 * 3) HW remove 12bit FMT support for DCE11 power saving reason.
55 FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED, in opp1_set_truncation()
56 FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, in opp1_set_truncation()
57 FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE); in opp1_set_truncation()
76 if (params->flags.FRAME_RANDOM == 1) { in opp1_set_spatial_dither()
77 if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) { in opp1_set_spatial_dither()
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
20 For old implementation efuses are parsed to select the correct opp table and
28 - qcom,apq8064
29 - qcom,apq8096
[all …]

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