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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
[all …]
/linux/drivers/mtd/nand/raw/ingenic/
H A Dingenic_nand_drv.c1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
38 unsigned int bank;
39 void __iomem *base; member
47 unsigned int num_banks;
58 unsigned int reading: 1;
71 static int qi_lb60_ooblayout_ecc(struct mtd_info *mtd, int section, in qi_lb60_ooblayout_ecc()
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc()
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/linux/drivers/mtd/nand/raw/
H A Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/mach-au1x00/au1000.h>
16 #include <asm/mach-au1x00/au1550nd.h>
23 int cs;
24 void __iomem *base; member
33 * au_write_buf - write buffer to chip
34 * @this: NAND chip object
41 unsigned int len) in au_write_buf()
45 int i; in au_write_buf()
48 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
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H A Dtechnologic-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Technologic Systems TS72xx NAND controller driver
35 void __iomem *base; member
45 static int ts72xx_nand_attach_chip(struct nand_chip *chip) in ts72xx_nand_attach_chip()
47 switch (chip->ecc.engine_type) { in ts72xx_nand_attach_chip()
49 return -EINVAL; in ts72xx_nand_attach_chip()
51 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in ts72xx_nand_attach_chip()
52 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
53 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
63 unsigned char bits = ioread8(data->ctrl) & ~GENMASK(2, 0); in ts72xx_nand_ctrl()
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H A Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
142 int steps;
143 unsigned int rdy_timeout_ms;
144 unsigned int len;
150 * struct anand - Defines the NAND chip related information
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H A Dgpio.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Device driver for NAND flash that uses a memory mapped interface to
11 * read/write the NAND commands and data, and GPIO pins for control signals
12 * (the DT binding refers to this as "GPIO assisted NAND flash")
25 #include <linux/mtd/nand-gpio.h>
31 struct nand_controller base; member
52 * Make sure the GPIO state changes occur in-order with writes to NAND
54 * Needed on PXA due to bus-reordering within the SoC itself (see section on
61 if (gpiomtd->io_sync) { in gpio_nand_dosync()
64 * What's required is what's here - a read from a separate in gpio_nand_dosync()
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H A Dnand_bbt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Bad block table support for the NAND driver
26 * For manufacturer created BBTs like the one found on M-SYS DOC devices
32 * number which indicates which of both tables is more up to date. If the NAND
52 * - bbts start at a page boundary, if autolocated on a block boundary
53 * - the space necessary for a bbt in FLASH does not exceed a block boundary
76 static inline uint8_t bbt_get_entry(struct nand_chip *chip, int block) in bbt_get_entry()
78 uint8_t entry = chip->bbt[block >> BBT_ENTRY_SHIFT]; in bbt_get_entry()
83 static inline void bbt_mark_entry(struct nand_chip *chip, int block, in bbt_mark_entry()
87 chip->bbt[block >> BBT_ENTRY_SHIFT] |= msk; in bbt_mark_entry()
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H A Dfsl_elbc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Freescale Enhanced Local Bus Controller NAND driver
4 * Copyright © 2006-2007, 2010 Freescale Semiconductor
9 * Roy Zang <tie-fei.zang@freescale.com>
41 int bank; /* Chip select bank number */
42 u8 __iomem *vbase; /* Chip select base virtual address */
43 int page_size; /* NAND page size (0=512, 1=2048) */
44 unsigned int fmr; /* FCM Flash Mode Register value */
54 unsigned int page; /* Last page written to / read from */
55 unsigned int read_bytes; /* Number of bytes read during command */
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H A Dams-delta.c1 // SPDX-License-Identifier: GPL-2.0
5 * Derived from drivers/mtd/nand/toto.c (removed in v2.6.28)
13 * This is a device driver for the NAND flash device found on the
22 #include <linux/mtd/nand-gpio.h>
33 struct nand_controller base; member
44 unsigned int tRP;
45 unsigned int tWP;
52 gpiod_set_value(priv->gpiod_nwe, 1); in gpio_nand_write_commit()
53 ndelay(priv->tWP); in gpio_nand_write_commit()
54 gpiod_set_value(priv->gpiod_nwe, 0); in gpio_nand_write_commit()
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H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * NAND Flash Controller Device Driver
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
295 * struct denali_chip_sel - per-CS data of Denali NAND
308 int bank;
320 * struct denali_chip - per-chip data of Denali NAND
322 * @chip: base NAND chip structure
325 * @sels: the array of per-cs data
330 unsigned int nsels;
335 * struct denali_controller - Denali NAND controller data
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H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
173 int irq;
178 int cur_cs;
189 int cs[1];
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H A Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
37 /* Max requests done for a 8k nand page size */
238 int ncs;
239 int cs_used[FMC2_MAX_CE];
250 int max_ncs;
251 int (*set_cdev)(struct stm32_fmc2_nfc *nfc);
255 struct nand_controller base; member
256 struct stm32_fmc2_nand nand; member
276 int dma_ecc_len;
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H A Dfsl_upm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale UPM NAND driver.
5 * Copyright © 2007-2008 MontaVista Software, Inc.
23 struct nand_controller base; member
42 static int fun_chip_init(struct fsl_upm_nand *fun, in fun_chip_init()
46 struct mtd_info *mtd = nand_to_mtd(&fun->chip); in fun_chip_init()
47 int ret; in fun_chip_init()
50 fun->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in fun_chip_init()
51 fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; in fun_chip_init()
52 fun->chip.controller = &fun->base; in fun_chip_init()
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H A Ddiskonchip.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de>
16 * Interface to generic NAND code for M-Systems DiskOnChip devices
61 struct nand_controller base; member
66 int chips_per_floor; /* The number of chips detected on each floor */
67 int curfloor;
68 int curchip;
69 int mh0_page;
70 int mh1_page;
76 int (*late_init)(struct mtd_info *mtd);
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H A Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
28 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
29 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
30 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
31 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
32 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
33 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
34 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
35 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
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H A Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
24 * nand commands
25 * The pins of the NAND chip are selected based on the address bits of the
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
71 static u8 xway_readb(struct mtd_info *mtd, int op) in xway_readb()
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H A Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale Integrated Flash Controller NAND driver
5 * Copyright 2011-2012 Freescale Semiconductor, Inc
25 for IFC NAND Machine */
35 int bank; /* Chip select bank number */
36 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
37 u8 __iomem *vbase; /* Chip select base virtual address */
46 unsigned int page; /* Last page written to / read from */
47 unsigned int read_bytes;/* Number of bytes read during command */
48 unsigned int column; /* Saved column from SEQIN */
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/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
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/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbcmbca_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
19 void __iomem *base; member
45 void __iomem *mmio = priv->base + BCMBCA_NAND_INT_STATUS; in bcmbca_nand_intc_ack()
60 void __iomem *mmio = priv->base + BCMBCA_NAND_INT_EN; in bcmbca_nand_intc_set()
72 void __iomem *flash_cache, u32 *buffer, int fc_words) in bcmbca_read_data_bus()
76 * and dest address, which is incompatible with nand cache. Fallback in bcmbca_read_data_bus()
85 static int bcmbca_nand_probe(struct platform_device *pdev) in bcmbca_nand_probe()
87 struct device *dev = &pdev->dev; in bcmbca_nand_probe()
93 return -ENOMEM; in bcmbca_nand_probe()
94 soc = &priv->soc; in bcmbca_nand_probe()
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H A Dbcm6368_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright 2000-2010 Broadcom Corporation
12 * Copyright 2000-2010 Broadcom Corporation
28 void __iomem *base; member
54 void __iomem *mmio = priv->base + BCM6368_NAND_INT; in bcm6368_nand_intc_ack()
72 void __iomem *mmio = priv->base + BCM6368_NAND_INT; in bcm6368_nand_intc_set()
86 static int bcm6368_nand_probe(struct platform_device *pdev) in bcm6368_nand_probe()
88 struct device *dev = &pdev->dev; in bcm6368_nand_probe()
94 return -ENOMEM; in bcm6368_nand_probe()
95 soc = &priv->soc; in bcm6368_nand_probe()
[all …]
/linux/arch/mips/rb532/
H A Ddevices.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <asm/mach-rc32434/rc32434.h>
25 #include <asm/mach-rc32434/dma.h>
26 #include <asm/mach-rc32434/dma_v.h>
27 #include <asm/mach-rc32434/eth.h>
28 #include <asm/mach-rc32434/rb.h>
29 #include <asm/mach-rc32434/integ.h>
30 #include <asm/mach-rc32434/gpio.h>
31 #include <asm/mach-rc32434/irq.h>
36 extern unsigned int idt_cpu_freq;
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/linux/drivers/memory/
H A Dfsl_ifc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 * convert_ifc_address - convert the base address
30 * @addr_base: base address of the memory bank
32 unsigned int convert_ifc_address(phys_addr_t addr_base) in convert_ifc_address()
39 * fsl_ifc_find - find IFC bank
40 * @addr_base: base address of the memory bank
42 * This function walks IFC banks comparing "Base address" field of the CSPR
47 int fsl_ifc_find(phys_addr_t addr_base) in fsl_ifc_find()
49 int i = 0; in fsl_ifc_find()
51 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs) in fsl_ifc_find()
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H A Djz4780-nemc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * JZ4780 NAND/external memory controller (NEMC)
6 * Author: Alex Smith <alex@alex-smith.me.uk>
20 #include <linux/jz4780-nemc.h>
22 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
42 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
43 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
44 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
54 void __iomem *base; member
61 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
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/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
20 unsigned int dma_low_channel;
21 unsigned int dma_high_channel;
26 * struct bch_geometry - BCH geometry description.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
43 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
49 unsigned int gf_len;
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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp4xx-reference-design.dtsi1 // SPDX-License-Identifier: ISC
5 * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
20 stdout-path = "uart0:115200n8";
28 compatible = "i2c-gpio";
29 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
30 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 * Philips PCF8582C-2T/03 512byte I2C EEPROM
43 read-only;
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