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Searched +full:mpc5121 +full:- +full:i2c (Results 1 – 10 of 10) sorted by relevance

/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * base MPC5121 Device Tree Source
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
13 model = "mpc5121";
14 compatible = "fsl,mpc5121";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
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H A Dmpc5125twr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
11 #include <dt-bindings/clock/mpc512x-clock.h>
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&ipic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
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H A Dpdm360ng.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2009 - 2010 DENX Software Engineering.
12 #include "mpc5121.dtsi"
16 compatible = "ifm,pdm360ng", "fsl,mpc5121";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&ipic>;
27 bank-width = <0x1>;
41 compatible = "amd,s29gl01gp", "cfi-flash";
44 #address-cells = <1>;
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H A Dmpc5121ads.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include "mpc5121.dtsi"
12 compatible = "fsl,mpc5121ads", "fsl,mpc5121";
32 compatible = "cfi-flash";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 bank-width = <4>;
37 device-width = <2>;
42 read-only;
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H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "mpc5121.dtsi"
13 compatible = "ifm,ac14xx", "fsl,mpc5121";
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - enum:
20 - mpc5200-i2c
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/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
20 #include <asm/mpc5121.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
83 * MPC5123 is an MPC5121 without the MBX graphics accelerator
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
102 if (of_machine_is_compatible("fsl,mpc5121")) { in mpc512x_clk_determine_soc()
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
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/linux/drivers/i2c/busses/
H A Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
25 #include <linux/i2c.h>
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) in writeccr() argument
114 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) in mpc_i2c_fixup() argument
127 for (k = 9; k; k--) { in mpc_i2c_fixup()
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/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
141 once-per-second update interrupts, used for synchronization.
159 will be called rtc-test.
161 comment "I2C RTC drivers"
163 if I2C
173 will be called rtc-88pm860x.
183 will be called rtc-88pm80x.
193 will be called rtc-88pm886.
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/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
107 to a single device like spi-nor (nvram), input device controller
166 supports spi-mem interface.
245 this code to manage the per-word or per-transfer accesses to the
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