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/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c27 #define IMX21LCDC_LSSAR 0x0000 /* LCDC Screen Start Address Register */
28 #define IMX21LCDC_LSR 0x0004 /* LCDC Size Register */
29 #define IMX21LCDC_LVPWR 0x0008 /* LCDC Virtual Page Width Register */
30 #define IMX21LCDC_LCPR 0x000C /* LCDC Cursor Position Register */
31 #define IMX21LCDC_LCWHB 0x0010 /* LCDC Cursor Width Height and Blink Register*/
32 #define IMX21LCDC_LCCMR 0x0014 /* LCDC Color Cursor Mapping Register */
33 #define IMX21LCDC_LPCR 0x0018 /* LCDC Panel Configuration Register */
34 #define IMX21LCDC_LHCR 0x001C /* LCDC Horizontal Configuration Register */
35 #define IMX21LCDC_LVCR 0x0020 /* LCDC Vertical Configuration Register */
36 #define IMX21LCDC_LPOR 0x0024 /* LCDC Panning Offset Register */
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/linux/Documentation/devicetree/bindings/display/
H A Datmel,lcdc.yaml4 $id: http://devicetree.org/schemas/display/atmel,lcdc.yaml#
7 title: Microchip's LCDC Framebuffer
14 The LCDC works with a framebuffer, which is a section of memory that contains
15 a complete frame of data representing pixel values for the display. The LCDC
22 - atmel,at91sam9261-lcdc
23 - atmel,at91sam9263-lcdc
24 - atmel,at91sam9g10-lcdc
25 - atmel,at91sam9g45-lcdc
26 - atmel,at91sam9g45es-lcdc
27 - atmel,at91sam9rl-lcdc
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H A Drenesas,shmobile-lcdc.yaml4 $id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml#
7 title: Renesas SH-Mobile LCD Controller (LCDC)
16 - renesas,r8a7740-lcdc # R-Mobile A1
17 - renesas,sh73a0-lcdc # SH-Mobile AG5
85 const: renesas,r8a7740-lcdc
96 const: renesas,sh73a0-lcdc
110 compatible = "renesas,r8a7740-lcdc";
H A Dmarvell,pxa2xx-lcdc.txt6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
25 compatible = "marvell,pxa2xx-lcdc";
H A Datmel,lcdc-display.yaml4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
7 title: Microchip's LCDC Display
14 The LCD Controller (LCDC) consists of logic for transferring LCD image data
15 from an external display buffer to a TFT LCD panel. The LCDC has one display
18 LCDC is programmable on a per layer basis, and supports different LCD
/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx-lcdc.yaml4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
25 - const: fsl,imx25-lcdc
26 - const: fsl,imx21-lcdc
66 LCDC Sharp Configuration Register value.
74 - fsl,imx1-lcdc
75 - fsl,imx21-lcdc
104 lcdc@53fbc000 {
105 compatible = "fsl,imx25-lcdc", "fsl,imx21-lcdc";
/linux/drivers/gpu/drm/tilcdc/
H A Dtilcdc_regs.h10 /* LCDC register definitions, based on da8xx-fb */
16 /* LCDC Status Register */
24 /* LCDC DMA Control Register */
39 /* LCDC Control Register */
44 /* LCDC Raster Control Register */
71 /* LCDC Raster Timing 2 Register */
83 /* LCDC Block */
H A Dtilcdc_crtc.c81 * unlikely that LCDC would fetch the DMA addresses in the middle of in set_scanout()
106 /* Tell the LCDC where the palette is located. */ in tilcdc_crtc_load_palette()
124 /* Enable LCDC DMA and wait for palette to be loaded. */ in tilcdc_crtc_load_palette()
133 /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */ in tilcdc_crtc_load_palette()
230 "failed to set the pixel clock - unable to read current lcdc clock rate\n"); in tilcdc_crtc_set_clk()
358 * be sure to set Bit 10 for the V2 LCDC controller, in tilcdc_crtc_set_mode()
1000 /* rev 1 lcdc appears to hang if irq is not disabled here */ in tilcdc_crtc_irq()
1008 /* Indicate to LCDC that the interrupt service routine has in tilcdc_crtc_irq()
H A Dtilcdc_drv.h31 /* Maximum display width for LCDC V1 */
33 /* ... and for LCDC V2 found on AM335x: */
/linux/arch/sh/include/asm/
H A Dsh7760fb.h3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
96 /* Display types supported by the LCDC */
120 /* LCDC Pixclock sources */
128 /* LCDC pixclock input divider. Set to 1 at a minimum! */
182 /* set this member to 1 if you wish to use the LCDC's hardware
192 * more than the LCDC in terms of blanking (e.g. disable clock
/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dtilcdc.txt8 - reg: base address and size of the LCDC device
11 - ti,hwmods: Name of the hwmod associated to the LCDC
21 This property deals with the LCDC revision 2 (found on AM335x)
41 tfp410 DVI encoder or lcd panel to lcdc
58 ti,hwmods = "lcdc";
/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_crtc.c218 dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n"); in atmel_hlcdc_crtc_atomic_disable()
224 dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n"); in atmel_hlcdc_crtc_atomic_disable()
231 dev_warn(dev->dev, "Atmel LCDC status register DISPSTS timeout\n"); in atmel_hlcdc_crtc_atomic_disable()
237 dev_warn(dev->dev, "Atmel LCDC status register LCDSTS timeout\n"); in atmel_hlcdc_crtc_atomic_disable()
243 dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n"); in atmel_hlcdc_crtc_atomic_disable()
272 dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n"); in atmel_hlcdc_crtc_atomic_enable()
278 dev_warn(dev->dev, "Atmel LCDC status register LCDSTS timeout\n"); in atmel_hlcdc_crtc_atomic_enable()
284 dev_warn(dev->dev, "Atmel LCDC status register DISPSTS timeout\n"); in atmel_hlcdc_crtc_atomic_enable()
291 dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n"); in atmel_hlcdc_crtc_atomic_enable()
297 dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n"); in atmel_hlcdc_crtc_atomic_enable()
H A Datmel_hlcdc_dc.h345 * @suspend.imr: used to read/write LCDC Interrupt Mask Register
366 * @update_lcdc_buffers: update the each LCDC layers DMA registers
367 * @lcdc_atomic_disable: disable LCDC interrupts and layers
368 * @lcdc_update_general_settings: update each LCDC layers general
370 * @lcdc_atomic_update: enable the LCDC layers and interrupts
373 * @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC layer
414 * @ops: atmel lcdc dc ops
/linux/Documentation/fb/
H A Dsh7760fb.rst2 SH7760/SH7763 integrated LCDC Framebuffer driver
7 The SH7760/SH7763 have an integrated LCD Display controller (LCDC) which
48 The LCDC must explicitly be told about the type of LCD panel
126 .name = "sh7760-lcdc",
/linux/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.h44 struct sh_mobile_lcdc_chan *lcdc; member
49 * struct sh_mobile_lcdc_chan - LCDC display channel
57 struct sh_mobile_lcdc_priv *lcdc; member
H A Dsh7760fb.c3 * SH7760/SH7763 LCDC Framebuffer driver.
69 /* en/disable the LCDC */
216 /* calculate LCDC reg vals from display parameters */ in sh7760fb_set_par()
248 /* shut down LCDC before changing display parameters */ in sh7760fb_set_par()
418 "unusable for the LCDC\n", (unsigned long)par->fbdma); in sh7760fb_alloc_mem()
476 "sh7760-lcdc", &par->vsync); in sh7760fb_probe()
511 strcpy(info->fix.id, "sh7760-lcdc"); in sh7760fb_probe()
574 .name = "sh7760-lcdc",
H A Datmel_lcdfb.c266 /* Wait for the LCDC core to become idle */ in atmel_lcdfb_stop_nowait()
576 /* Now, the LCDC core... */ in atmel_lcdfb_set_par()
877 { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
878 { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
879 { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
880 { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
881 { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
882 { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
1067 /* Enable LCDC Clocks */ in atmel_lcdfb_probe()
1131 /* LCDC registers */ in atmel_lcdfb_probe()
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Datmel,hlcdc-pwm.yaml15 The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block
20 values for PWM frequency. If the LCDC PWM frequency range does not match the
/linux/Documentation/devicetree/bindings/display/atmel/
H A Datmel,hlcdc-display-controller.yaml15 The LCD Controller (LCDC) consists of logic for transferring LCD image
16 data from an external display buffer to a TFT LCD panel. The LCDC has one
/linux/arch/sh/boards/mach-se/7722/
H A Dsetup.c160 /* LCDC I/O */ in se7722_setup()
168 /* LCDC */ in se7722_setup()
173 __raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */ in se7722_setup()
/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c27 USB, LCDC, enumerator
56 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
90 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
111 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh770x.c30 LCDC, PCC0, PCC1, enumerator
62 INTC_VECT(LCDC, 0x9a0),
83 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,lvds.yaml53 const: lcdc
138 pinctrl-names = "lcdc";
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7366.c267 VEU2, LCDC, enumerator
302 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
325 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
347 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
H A Dsetup-sh7734.c326 LCDC, enumerator
415 INTC_VECT(LCDC, 0xC40),
451 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
483 LCDC_M, /* LCDC, MIMLB */
509 { SCIF0, SCIF3, HSCIF, LCDC } },

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