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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-cadence.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
[all …]
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
[all …]
H A Dqcom,ebi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
20 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
28 memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc770-xm011.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
22 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
42 clock-frequency = <400000>;
52 num-cs = <4>;
[all …]
H A Dzynq-zc770-xm012.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
38 clock-frequency = <400000>;
48 clock-frequency = <400000>;
58 num-cs = <4>;
59 is-decoded-cs = <0>;
H A Dzynq-zc770-xm013.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
38 phy-mode = "rgmii-id";
39 phy-handle = <&ethernet_phy>;
41 ethernet_phy: ethernet-phy@7 {
43 device_type = "ethernet-phy";
49 clock-frequency = <400000>;
[all …]
H A Dzynq-zc770-xm010.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
43 phy-mode = "rgmii-id";
44 phy-handle = <&ethernet_phy>;
[all …]
/linux/arch/x86/lib/
H A Dinsn-eval.c14 #include <asm/insn-eval.h>
29 * is_string_insn() - Determine if instruction is a string instruction
34 * true if the instruction, determined by the opcode, is any of the
40 /* All string instructions have a 1-byte opcode. */ in is_string_insn()
41 if (insn->opcode.nbytes != 1) in is_string_insn()
44 switch (insn->opcode.bytes[0]) { in is_string_insn()
55 * insn_has_rep_prefix() - Determine if instruction has a REP prefix
78 * get_seg_reg_override_idx() - obtain segment register override index
85 * A constant identifying the segment register to use, among CS, SS, DS,
86 * ES, FS, or GS. INAT_SEG_REG_DEFAULT is returned if no segment override
[all …]
/linux/arch/x86/realmode/rm/
H A Dreboot.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/processor-flags.h>
7 #include <asm/msr-index.h>
14 * controller to pulse the CPU reset line, which is more thorough, but
15 * doesn't work with at least one type of 486 motherboard. It is easy
18 * This code is called with the restart type (0 = BIOS, 1 = APM) in
26 /* Switch to trampoline GDT as it is guaranteed < 4 GiB */
52 * mode. The GDT is not used in real mode; it is just needed here to
58 * Load the data segment registers with 16-bit compatible values
70 * This is 16-bit protected mode code to disable paging and the cache,
[all …]
/linux/include/media/
H A Dv4l2-jpeg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * For reference, see JPEG ITU-T.81 (ISO/IEC 10918-1)
13 #include <linux/v4l2-controls.h>
35 /* Length of reference huffman tables as provided in Table K.3 of ITU-T.81 */
43 * struct v4l2_jpeg_reference - reference into the JPEG buffer
48 * and length is the size of the segment parameters, excluding the marker code.
58 * struct v4l2_jpeg_frame_component_spec - frame component-specification
72 * struct v4l2_jpeg_frame_header - JPEG frame header
77 * @component: component-specification, see v4l2_jpeg_frame_component_spec
78 * @subsampling: decoded subsampling from component-specification
[all …]
/linux/drivers/isdn/mISDN/
H A Ddsp_blowfish.c17 * how to encode a sample stream to 64-bit blocks that will be encryped
19 * first of all, data is collected until a block of 9 samples are received.
20 * of course, a packet may have much more than 9 sample, but is may have
21 * not excacly the multiple of 9 samples. if there is a rest, the next
24 * the block is then converted to 9 uLAW samples without the least sigificant
25 * bit. the result is a 7-bit encoded sample.
39 * the missing bit 0 of the last byte is filled with some
44 * the result will be converted into 9 bytes. the bit 7 is used for
45 * checksumme (CS) for sync (0, 1) and for the last bit:
53 * CS 4(4) 4(3) 4(2) 4(1) 4(0) 5(7) 5(6)
[all …]
/linux/tools/perf/util/
H A Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2015-2018 Linaro Limited.
12 #include <linux/coresight-pmu.h>
22 #include "cs-etm.h"
23 #include "cs-etm-decode
[all...]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c1 // SPDX-License-Identifier: MIT
24 * The per-platform tables are u8-encoded in @data. Decode @data and set the
25 * addresses' offset and commands in @regs. The following encoding is used
29 * [7]: create NOPs - number of NOPs are set in lower bits
35 * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"
37 * is used for offsets smaller than 0x200 while the latter is for values bigger
60 const u32 base = engine->mmio_base; in set_offsets()
78 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
95 } while (--count); in set_offsets()
101 if (GRAPHICS_VER(engine->i915) >= 11) in set_offsets()
[all …]
/linux/drivers/atm/
H A Dfore200e.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE)…
56 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
61 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
65 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
66 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
256 OPCODE_SET_OC3, /* set OC-3 registers */
257 OPCODE_GET_OC3, /* get OC-3 registers */
260 OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the
318 /* OC-3 registers */
[all …]
/linux/drivers/spi/
H A Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
68 u8 cs; member
314 if (ret != -ETIMEDOUT) in cqspi_wait_for_bit()
[all …]
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
25 #define CDNS_SPI_NAME "cdns-spi"
63 * SPI Configuration Register - Baud rate and target select
93 * This register is used to enable or disable the SPI controller
102 * struct cdns_spi - This definition defines spi driver instance
136 return readl_relaxed(xspi->regs + offset); in cdns_spi_read()
141 writel_relaxed(val, xspi->regs + offset); in cdns_spi_write()
145 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
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/linux/fs/nfsd/
H A Dxdr4.h2 * Server-side types for NFSv4.
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
49 #define SET_CSTATE_FLAG(c, f) ((c)->sid_flags |= (f))
50 #define HAS_CSTATE_FLAG(c, f) ((c)->sid_flags & (f))
51 #define CLEAR_CSTATE_FLAG(c, f) ((c)->sid_flags &= ~(f))
54 * nfsd4_encode_bool - Encode an XDR bool type result
74 * nfsd4_encode_uint32_t - Encode an XDR uint32_t type result
104 * nfsd4_encode_uint64_t - Encode an XDR uint64_t type result
129 * nfsd4_encode_opaque_fixed - Encode a fixed-length XDR opaque type result
154 * nfsd4_encode_opaque - Encode a variable-length XDR opaque type result
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
7 * Additional technical information is available on
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * BBT table is not serialized, has to be fixed
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
[all …]
/linux/arch/x86/kvm/svm/
H A Dsvm.c18 #include <linux/amd-iommu.h>
24 #include <linux/psp-sev.h>
39 #include <asm/spec-ctrl.h>
56 MODULE_DESCRIPTION("KVM support for SVM (AMD-V) extensions");
86 bool always; /* True if intercept is initially cleared */
132 * AMD does not virtualize APIC TSC-deadline timer mode, but it is
149 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
152 * count value. On VMRUN this value is loaded into an internal counter.
153 * Each time a pause instruction is executed, this counter is decremented
154 * until it reaches zero at which time a #VMEXIT is generated if pause
[all …]
/linux/arch/x86/kernel/
H A Duprobes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * User-space Probes (UProbes) for x86
5 * Copyright (C) IBM Corporation, 2008-2011
22 /* Post-execution fixups. */
42 #define OPCODE1(insn) ((insn)->opcode.bytes[0])
43 #define OPCODE2(insn) ((insn)->opcode.bytes[1])
44 #define OPCODE3(insn) ((insn)->opcode.bytes[2])
45 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
55 * Good-instruction tables for 32-bit apps. This is non-const and volatile
57 * some versions of gcc to think only *(unsigned long*) is used.
[all …]
/linux/fs/nfs/
H A Dnfs2xdr.c1 // SPDX-License-Identifier: GPL-2.0
9 * 04 Aug 1998 Ion Badulescu <ionut@cs.columbia.edu>
33 * number of 32bit-words
72 * functions. For run-time efficiency, some data types are encoded
73 * or decoded inline.
78 if (clnt && clnt->cl_cred) in rpc_userns()
79 return clnt->cl_cred->user_ns; in rpc_userns()
85 if (rqstp->rq_task) in rpc_rqst_userns()
86 return rpc_userns(rqstp->rq_task->tk_client); in rpc_rqst_userns()
100 return -EIO; in decode_nfsdata()
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_lrc.c1 // SPDX-License-Identifier: MIT
62 return gt_to_xe(lrc->fence_ctx.gt); in lrc_to_xe()
102 * The per-platform tables are u8-encoded in @data. Decode @data and set the
103 * addresses' offset and commands in @regs. The following encoding is used
107 * [7]: create NOPs - number of NOPs are set in lower bits
113 * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"
115 * is used for offsets smaller than 0x200 while the latter is for values bigger
137 const u32 base = hwe->mmio_base; in set_offsets()
158 xe_gt_assert(hwe->gt, count); in set_offsets()
171 } while (--count); in set_offsets()
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
138 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
139 * If DSP_MB_DELAY == 1, MB delay is DSP_MB_DELAY * 128
147 /* DDR-DPR Burst Read Enable */
[all …]
/linux/drivers/edac/
H A Di10nm_base.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <asm/intel-family.h>
24 pci_read_config_dword((d)->uracu, 0xd0, &(reg))
26 pci_read_config_dword((d)->uracu, \
27 (res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg))
29 pci_read_config_dword((d)->sad_all, (offset) + (i) * \
30 (res_cfg->type == GNR ? 12 : 8), &(reg))
32 pci_read_config_dword((d)->uracu, 0xd4, &(reg))
34 pci_read_config_dword((d)->pcu_cr3, \
35 res_cfg->type == GNR ? 0x290 : 0x90, &(reg))
[all …]

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