Lines Matching +full:is +full:- +full:decoded +full:- +full:cs
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
138 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
139 * If DSP_MB_DELAY == 1, MB delay is DSP_MB_DELAY * 128
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
197 * set, the output video is interlaced (stripy).
203 * De-interlacer Mode
205 * 0 Normal Un-Shuffled Frame
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
241 * 0 DSP_SKIP_OFFSET value is not used (default 8)
242 * 1 DSP_SKIP_OFFSET value is used in HW
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
422 * Swap byte order of VLC stream in d-word.
452 * 1 VLC is ready in buffer n (HW set)
453 * 0 VLC is not ready in buffer n (SW clear)
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
499 * A word is 4 bytes. I.e.,
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
641 * The register is applicable to PCI initiator mode only. Used to select PCM(0)
653 * When PCI_FLOW_EN is set, PCI need to toggle this bit to send an audio frame
658 /* [1:0] CS valid to data valid CLK cycles when writing operation */
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
701 * frequency is controlled with the following equation.
804 * Become valid after sync to the xtal clock domain. This bit is set only if
805 * LOAD register bit is also set to 1.
811 * LOAD register bit is also set to 1.
817 * the LOAD register bit is also set to 1.
822 * clock domain to restart the PLL. This bit is self cleared.
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
856 * 1 Interrupt output is high assertion
857 * 0 Interrupt output is low assertion
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
933 * H264EN_CH_PROG[n] H264 Encoding Path channel n is progressive
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1000 /* This register is not defined in datasheet, but used in reference driver */
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1015 * [2:0] Data valid counter after read command to DDR. This is the delay value
1025 * default is 7
1030 * default is 4"hf
1036 * period, default is 4"h2
1040 /* Twr value, write recovery time, default is 4"h3 */
1046 * availability of the first bit of output data, default is 3
1050 * [15:0] Maximum average periodic refresh, the value is based on the current
1068 * 1 DDR self-test mode
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1115 /* [15:0] Default is C013 */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1151 * In order to access the indirect register space, the following procedure is
1158 * (2) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1161 * (1) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1163 * (3) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1170 /* Wait until this bit is "0" before using indirect access */
1172 /* Activate the indirect access. This bit is self cleared */
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1229 * 0 MV is saved in internal DPR
1230 * 1 MV is saved in DDR
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1286 * registers to indicate interrupt status for every channels. This is secondary
1287 * interrupt status register. OR operating of the PREV_INTR_REG is
1288 * PREV_EOF_INTR, OR operating of the AU_INTR_REG bits is AUDIO_EOF_INTR
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1313 * this register is the buffer flag to notify software which buffer is been
1351 /* vlc stream crc value, it is calculated in pci module */
1354 * vlc max length, it is defined by software based on software assign memory
1364 /* mv stream crc value, it is calculated in pci module */
1394 * The above register is pci base address registers. Application software will
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1419 /* Begin a new DDR Burst. This bit is self cleared */
1444 /* 0x84000 - 0x87ffc */
1449 * The indirect space is accessed through 0xb800 ~ 0xb807 registers in direct
1454 /* Read-only register */
1458 * 1 Video not present. (sync is not detected in number of consecutive line
1464 * 1 Horizontal sync PLL is locked to the incoming video source.
1465 * 0 Horizontal sync PLL is not locked.
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1474 * 1 Even field is being decoded.
1475 * 0 Odd field is being decoded.
1479 * 1 Vertical logic is locked to the incoming video source.
1480 * 0 Vertical logic is not locked.
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505 * 0 = Non-standard signal
1506 * Read-only
1510 * 1 = Non-interlaced signal
1512 * Read-only
1542 * active pixel for display / record path. A unit is 1 pixel. The default value
1543 * is 0x00f for NTSC and 0x00a for PAL.
1546 * for display / record path. A unit is 1 pixel. The default value is decimal
1550 * active for display / record path. A unit is 1 line. The default value is
1554 * for display / record path. A unit is 1 line. The default value is decimal
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1561 * purplish tone. The default value is 0o (00h). This is effective only on NTSC
1562 * system. The default is 00h.
1570 * The corresponding gain adjustment is HFLT.
1575 /* CTI level selection. The default is 1.
1586 * strongest. The default is 1.
1592 * gain of 1. The range adjustment is from 0% to 255% at 1% per step. The
1593 * default is 64h.
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1600 * effect on the data. The default is 00h.
1609 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1610 * gain of 100%. The default is 80h.
1619 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1620 * gain of 100%. The default is 80h.
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1634 * This bit is valid only when color stripe protection is detected, i.e. if
1641 /* Read-only */
1645 * Read-only.
1687 * process. This bit is a self-clearing bit
1688 * 0 Manual initiation of auto format detection is done. (Default)
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1748 * 1 SB (Signed MSB bit in PCM data is inverted) output
1749 * 2 u-Law output
1750 * 3 A-Law output
1761 * Enable the mute function for audio channel AINn when n is 0 to 3. It effects
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1794 * This mode is only effective when ACLKRMASTER=1
1796 * 1 ACKI control is automatically set up by AFMD register values
1819 * 0 High periods is one 27MHz clock period (default).
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1822 * AFAUTO=1, ACKI control is automatically set up even if MASCKMD=1.
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1841 * 0 No delay (Default). This is for I2S type 1T delay input interface.
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1849 * 1 SB (Signed MSB bit in PCM data is inverted) input
1850 * 2 u-Law input
1851 * 3 A-Law input
1864 * [7:3]: DEV_ID The TW5864 product ID code is 01000
1865 * [2:0]: REV_ID The revision number is 0h
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1928 /* valid value for channel is [0:15] */
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2013 * Large value is suitable for slow motion detection.
2060 * [11:0] The base address of the motion detection buffer. This address is in
2088 * [9:0] The motion cell count of a specific channel selected by 0x382. This is