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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53573.dtsi8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 {
43 #interrupt-cells = <3>;
45 interrupt-controller;
78 #interrupt-cells = <1>;
79 interrupt-map-mask = <0x000fffff 0xffff>;
80 interrupt-map =
121 interrupt-parent = <&gic>;
[all …]
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml125 interrupt-controller:
127 $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
154 - interrupt-controller
176 cpu_intc0: interrupt-controller {
177 #interrupt-cells = <1>;
179 interrupt-controller;
202 cpu_intc1: interrupt-controller {
203 #interrupt-cells = <1>;
205 interrupt-controller;
223 interrupt-controller {
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/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml36 interrupt-names:
119 - "#interrupt-cells"
121 - interrupt-names
122 - interrupt-map-mask
123 - interrupt-map
128 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
189 #include <dt-bindings/interrupt-controller/irq.h>
190 #include <dt-bindings/interrupt-controller/arm-gic.h>
201 #interrupt-cells = <1>;
204 interrupt-names = "pcie", "msi";
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H A Dsifive,fu740-pcie.yaml42 interrupt-names:
71 - interrupt-names
72 - interrupt-map-mask
73 - interrupt-map
93 #interrupt-cells = <1>;
107 interrupt-names = "msi", "inta", "intb", "intc", "intd";
108 interrupt-parent = <&plic0>;
109 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
110 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A De1000e.rst52 Interrupt Throttle Rate controls the number of interrupts each interrupt
58 per second, even if more packets have come in. This reduces interrupt
66 for this reason an adaptive interrupt moderation algorithm was implemented.
83 Turns off any interrupt moderation and may improve small packet latency.
85 to the increased CPU utilization of the higher interrupt rate.
98 In simplified mode the interrupt rate is based on the ratio of TX and
100 interrupt rate will drop as low as 2000 interrupts per second. If the
101 traffic is mostly transmit or mostly receive, the interrupt rate could
106 even if more packets have come in. This reduces interrupt load on the
113 interrupts than what the Interrupt Throttle Rate allows.
[all …]
/linux/arch/powerpc/boot/dts/
H A Dstorcenter.dts66 interrupt-parent = <&mpic>;
82 interrupt-parent = <&mpic>;
93 interrupt-parent = <&mpic>;
96 mpic: interrupt-controller@40000 {
97 #interrupt-cells = <2>;
101 interrupt-controller;
110 #interrupt-cells = <1>;
118 interrupt-parent = <&mpic>;
119 interrupt-map-mask = <0xf800 0 0 7>;
120 interrupt-map = <
/linux/drivers/net/can/rcar/
H A Drcar_can.c11 #include <linux/interrupt.h>
57 u32 mier1; /* Mailbox Interrupt Enable Register 1 */
60 u32 mier0; /* Mailbox Interrupt Enable Register 0 */
71 u8 eier; /* Error Interrupt Enable Register */
72 u8 eifr; /* Error Interrupt Factor Judge Register */
84 u8 ier; /* Interrupt Enable Register */
85 u8 isr; /* Interrupt Status Register */
162 /* Mailbox Interrupt Enable Register 1 bits */
163 #define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */
164 #define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dsprd,gpio-eic.yaml16 The EIC is the abbreviation of external interrupt controller, which can
85 interrupt-controller: true
87 "#interrupt-cells":
93 The interrupt shared by all GPIO lines for this controller.
100 - interrupt-controller
101 - "#interrupt-cells"
108 #include <dt-bindings/interrupt-controller/arm-gic.h>
119 interrupt-controller;
120 #interrupt-cells = <2>;
H A Dnvidia,tegra20-gpio.yaml31 description: The interrupt outputs from the controller. For Tegra20,
45 "#interrupt-cells":
59 interrupt-controller: true
84 - "#interrupt-cells"
85 - interrupt-controller
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
108 #interrupt-cells = <2>;
109 interrupt-controller;
H A Dfsl-imx-gpio.yaml61 Should be the port interrupt shared by all 32 pins, if one number.
62 If two numbers, the first one is the interrupt shared by low 16 pins
67 interrupt-controller: true
69 "#interrupt-cells":
95 - interrupt-controller
96 - "#interrupt-cells"
110 interrupt-controller;
111 #interrupt-cells = <2>;
H A Datmel,at91rm9200-gpio.yaml34 interrupt-controller: true
36 "#interrupt-cells":
58 - interrupt-controller
59 - "#interrupt-cells"
69 #include <dt-bindings/interrupt-controller/irq.h>
77 interrupt-controller;
78 #interrupt-cells = <2>;
/linux/arch/mips/boot/dts/mscc/
H A Dserval.dtsi28 cpuintc: interrupt-controller {
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
55 interrupt-parent = <&intc>;
62 intc: interrupt-controller@70000070 {
65 #interrupt-cells = <1>;
66 interrupt-controller;
67 interrupt-parent = <&cpuintc>;
/linux/Documentation/devicetree/bindings/misc/
H A Dpci1de4,1.yaml28 '#interrupt-cells':
31 Specifies respectively the interrupt number and flags as defined
32 in include/dt-bindings/interrupt-controller/irq.h.
35 The supported values for the interrupt number are:
98 interrupt-controller: true
104 - '#interrupt-cells'
105 - interrupt-controller
119 interrupt-controller;
120 #interrupt-cells = <2>;
/linux/kernel/irq/
H A Dmsi.c145 * @domid: The id of the interrupt domain to which the desriptor is added
389 * @domid: The id of the interrupt domain which should be walked.
416 * @domid: The id of the interrupt domain which should be walked.
446 * msi_domain_get_virq - Lookup the Linux interrupt number for a MSI index on a interrupt domain
448 * @domid: Domain ID of the interrupt domain associated to the device
449 * @index: MSI interrupt index to look for (0-based)
451 * Return: The Linux interrupt number on success (> 0), 0 if not found
476 * interrupt. in msi_domain_get_virq()
505 /* MSI vs. MSIX is per device not per interrupt */ in msi_mode_show()
655 * @irq_data: The irq data associated to the interrupt
[all …]
/linux/drivers/comedi/drivers/
H A Daddi_apci_1032.c29 * interrupts (if an interrupt handler can be set up successfully).
33 * Change-Of-State (COS) interrupt configuration:
40 * - interrupt is generated when any enabled channel meets the desired
41 * interrupt condition
45 * - interrupt is generated when all enabled channels meet the desired
46 * interrupt condition
47 * - after an interrupt, a change in level must occur on the selected
65 #include <linux/interrupt.h>
87 unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
94 /* Reset the interrupt status register */ in apci1032_reset()
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-icicle-kit-fabric.dtsi23 interrupt-parent = <&plic>;
32 #interrupt-cells = <0x1>;
39 interrupt-parent = <&plic>;
41 interrupt-map = <0 0 0 1 &pcie_intc 0>,
45 interrupt-map-mask = <0 0 0 7>;
53 pcie_intc: interrupt-controller {
55 #interrupt-cells = <1>;
56 interrupt-controller;
H A Dmpfs-polarberry-fabric.dtsi20 #interrupt-cells = <0x1>;
27 interrupt-parent = <&plic>;
29 interrupt-map = <0 0 0 1 &pcie_intc 0>,
33 interrupt-map-mask = <0 0 0 7>;
40 pcie_intc: interrupt-controller {
42 #interrupt-cells = <1>;
43 interrupt-controller;
H A Dmpfs-m100pfs-fabric.dtsi20 #interrupt-cells = <0x1>;
27 interrupt-parent = <&plic>;
29 interrupt-map = <0 0 0 1 &pcie_intc 0>,
33 interrupt-map-mask = <0 0 0 7>;
40 pcie_intc: interrupt-controller {
42 #interrupt-cells = <1>;
43 interrupt-controller;
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml53 interrupt-controller: true
55 "#interrupt-cells":
59 third cell is the interrupt type.
70 - interrupt-controller
71 - "#interrupt-cells"
78 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 interrupt-controller;
86 #interrupt-cells = <3>;
/linux/sound/arm/
H A Daaci.h35 #define AACI_SLISTAT 0x06c /* slot interrupt status */
36 #define AACI_SLIEN 0x070 /* slot interrupt enable */
37 #define AACI_INTCLR 0x074 /* interrupt clear */
41 #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
88 * interrupt status register bits.
99 * interrupt enable register bits.
110 * interrupt status. P51
115 #define ISR_RX (1 << 3) /* rx interrupt status */
116 #define ISR_TX (1 << 2) /* tx interrupt status */
121 * interrupt enable. P52
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h35 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
36 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
37 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
38 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
50 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
51 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
60 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
62 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
63 Rising Edge Interrupt Enable */
64 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
[all …]
/linux/arch/arc/boot/dts/
H A Dvdk_axc003.dtsi32 interrupt-controller;
33 #interrupt-cells = <1>;
40 interrupt-parent = <&core_intc>;
49 mb_intc: interrupt-controller@e0012000 {
50 #interrupt-cells = <1>;
53 interrupt-controller;
54 interrupt-parent = <&core_intc>;
/linux/Documentation/devicetree/bindings/net/
H A Dbtusb.txt21 - interrupt-names: (see below)
22 - interrupts : The interrupt specified by the name "wakeup" is the interrupt
24 request this interrupt for wakeup. During system suspend, the
27 disabled to make sure unnecessary interrupt is not received.
40 interrupt-parent = <&gpio0>;
41 interrupt-names = "wakeup";
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1.dtsi9 #include <dt-bindings/interrupt-controller/irq.h>
34 aitc: aitc-interrupt-controller@223000 {
36 interrupt-controller;
37 #interrupt-cells = <1>;
68 interrupt-parent = <&aitc>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
238 interrupt-controller;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7981b.dtsi4 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
50 gic: interrupt-controller@c000000 {
54 interrupt-parent = <&gic>;
56 interrupt-controller;
57 #interrupt-cells = <3>;
101 interrupt-names = "uart", "wakeup";
112 interrupt-names = "uart", "wakeup";
123 interrupt-names = "uart", "wakeup";
200 interrupt-controller;
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