| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | mti,cpu-interrupt-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
7 title: MIPS CPU Interrupt Controller
14 platforms internal interrupt controller cascade.
21 const: mti,cpu-interrupt-controller
23 '#interrupt-cells':
29 interrupt-controller: true
35 - '#interrupt-cells'
37 - interrupt-controller
41 interrupt-controller {
42 compatible = "mti,cpu-interrupt-controller";
[all …]
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| H A D | ralink,rt2880-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ralink,rt2880-intc.yaml#
7 title: Ralink SoCs Interrupt Controller
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller support a central point for interrupt aggregation
29 interrupt-controller: true
31 '#interrupt-cells':
38 - interrupt-controller
39 - '#interrupt-cells'
45 interrupt-controller@200 {
48 interrupt-controller;
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| H A D | mstar,mst-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
7 title: MStar Interrupt Controller
14 interrupt controllers that routes interrupts to the GIC.
16 The HW block exposes a number of interrupt controllers, each
23 interrupt-controller: true
25 "#interrupt-cells":
35 The range <start, end> of parent interrupt controller's interrupt
36 lines that are hardwired to mstar interrupt controller.
44 Mark this controller has no End Of Interrupt(EOI) implementation.
56 mst_intc0: interrupt-controller@1f2032d0 {
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| H A D | renesas,rza1-irqc.txt | 1 DT bindings for the Renesas RZ/A1 Interrupt Controller
3 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
15 - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
18 - interrupt-controller: Marks the device as an interrupt controller
19 - reg: Base address and length of the memory resource used by the interrupt
21 - interrupt-map: Specifies the mapping from external interrupts to GIC
23 - interrupt-map-mask: Must be <7 0>
27 irqc: interrupt-controller@fcfef800 {
29 #interrupt-cells = <2>;
31 interrupt-controller;
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| H A D | samsung,s3c24xx-irq.txt | 1 Samsung S3C24XX Interrupt Controllers
3 The S3C24XX SoCs contain a custom set of interrupt controllers providing a
4 varying number of interrupt sources. The set consists of a main- and sub-
14 - interrupt-controller : Identifies the node as an interrupt controller
16 - #interrupt-cells : Specifies the number of cells needed to encode an
17 interrupt source. The value shall be 4 and interrupt descriptor shall
27 ctrl_irq contains the interrupt bit of the controller
32 interrupt-controller@4a000000 {
35 interrupt-controller;
36 #interrupt-cells=<4>;
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| H A D | actions,owl-sirq.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
7 title: Actions Semi Owl SoCs SIRQ interrupt controller
14 This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
15 and S900) and provides support for handling up to 3 external interrupt lines.
27 interrupt-controller: true
29 '#interrupt-cells':
33 cell is the trigger type as defined in interrupt.txt in this directory.
37 Contains the GIC SPI IRQs mapped to the external interrupt lines.
45 - interrupt-controller
46 - '#interrupt-cells'
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| H A D | arm,nvic.txt | 1 * ARM Nested Vector Interrupt Controller (NVIC)
3 The NVIC provides an interrupt controller that is tightly coupled to
5 vary in the number of interrupts and priority bits per interrupt.
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
15 interrupt source. The type shall be a <u32> and the value shall be 2.
17 The 1st cell contains the interrupt number for the interrupt type.
19 The 2nd cell is the priority of the interrupt.
29 intc: interrupt-controller@e000e100 {
31 #interrupt-cells = <2>;
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| H A D | loongarch,cpu-interrupt-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
7 title: LoongArch CPU Interrupt Controller
14 const: loongarch,cpu-interrupt-controller
16 '#interrupt-cells':
19 interrupt-controller: true
25 - '#interrupt-cells'
26 - interrupt-controller
30 interrupt-controller {
31 compatible = "loongarch,cpu-interrupt-controller";
32 #interrupt-cells = <1>;
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| H A D | loongson,cpu-interrupt-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,cpu-interrupt-controller.yaml#
7 title: LoongArch CPU Interrupt Controller
14 const: loongson,cpu-interrupt-controller
16 '#interrupt-cells':
19 interrupt-controller: true
25 - '#interrupt-cells'
26 - interrupt-controller
30 interrupt-controller {
31 compatible = "loongson,cpu-interrupt-controller";
32 #interrupt-cells = <1>;
[all …]
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| H A D | loongson,htvec.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
7 title: Loongson-3 HyperTransport Interrupt Vector Controller
13 This interrupt controller is found in the Loongson-3 family of chips for
14 receiving vectorized interrupts from PCH's interrupt controller.
28 interrupt-controller: true
30 '#interrupt-cells':
37 - interrupt-controller
38 - '#interrupt-cells'
44 #include <dt-bindings/interrupt-controller/irq.h>
45 htvec: interrupt-controller@fb000080 {
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| H A D | loongson,eiointc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,eiointc.yaml#
7 title: Loongson Extended I/O Interrupt Controller
13 This interrupt controller is found on the Loongson-3 family chips and
15 individual cores without forwarding them through the HT's interrupt line.
18 - $ref: /schemas/interrupt-controller.yaml#
32 interrupt-controller: true
34 '#interrupt-cells':
41 - interrupt-controller
42 - '#interrupt-cells'
48 eiointc: interrupt-controller@1fe11600 {
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| H A D | brcm,bcm2836-l1-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
7 title: BCM2836 per-CPU interrupt controller
14 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
16 peripheral (GPU) events, which chain to the BCM2835-style interrupt
20 - $ref: /schemas/interrupt-controller.yaml#
29 interrupt-controller: true
31 '#interrupt-cells':
37 - interrupt-controller
38 - '#interrupt-cells'
44 local_intc: interrupt-controller@40000000 {
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| H A D | qcom,pdc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
7 title: PDC interrupt controller
16 interrupt controller that can be used to help detect edge low interrupts as
19 GIC is parent interrupt controller at the highest level. Platform interrupt
22 specify PDC as their interrupt controller and request the PDC port associated
23 with the GIC interrupt. See example below.
58 '#interrupt-cells':
61 interrupt-controller: true
80 - '#interrupt-cells'
81 - interrupt-controller
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| H A D | loongson,htpic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
7 title: Loongson-3 HyperTransport Interrupt Controller
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
32 interrupt-controller: true
34 '#interrupt-cells':
41 - interrupt-controller
42 - '#interrupt-cells'
48 #include <dt-bindings/interrupt-controller/irq.h>
49 htintc: interrupt-controller@1fb000080 {
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| /freebsd/sys/contrib/device-tree/src/arm64/apple/ |
| H A D | t600x-die0.dtsi | 17 aic: interrupt-controller@28e100000 {
19 #interrupt-cells = <4>;
20 interrupt-controller;
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 interrupt-parent = <&aic>;
52 interrupt-parent = <&aic>;
59 interrupt-parent = <&aic>;
68 interrupt-parent = <&aic>;
87 interrupt-parent = <&aic>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | tc3589x.txt | 18 - interrupts : the interrupt on the parent the controller is connected to
19 - interrupt-controller : marks the device node as an interrupt controller
20 - #interrupt-cells : should be <1>, the first cell is the IRQ offset on this
21 TC3589x interrupt controller.
29 - interrupts : interrupt on the parent, which must be the tc3589x MFD device
30 - interrupt-controller : marks the device node as an interrupt controller
31 - #interrupt-cells : should be <2>, the first cell is the IRQ offset on this
32 TC3589x GPIO interrupt controller, the second cell is the interrupt flags
33 in accordance with <dt-bindings/interrupt-controller/irq.h>. The following
65 interrupt-parent = <&gpio6>;
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| /freebsd/sys/contrib/device-tree/Bindings/cpufreq/ |
| H A D | brcm,stb-avs-cpu-freq.txt | 1 Broadcom AVS mail box and interrupt register bindings
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
11 The interface also requires a reference to the AVS host interrupt controller,
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
30 - interrupts: The interrupt that the AVS CPU will use to interrupt the host
32 - interrupt-names: The name of the interrupt used to interrupt the host.
53 avs_host_l2_intc: interrupt-controller@f04d1200 {
54 #interrupt-cells = <1>;
56 interrupt-parent = <&intc>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
| H A D | bcm7445.dtsi | 2 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
48 gic: interrupt-controller@ffd00000 {
54 interrupt-controller;
55 #interrupt-cells = <3>;
99 irq0_intc: interrupt-controller@40a780 {
101 interrupt-parent = <&gic>;
102 #interrupt-cells = <1>;
104 interrupt-controller;
111 irq0_aon_intc: interrupt-controller@417280 {
[all …]
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| /freebsd/sys/dts/arm/ |
| H A D | vybrid.dtsi | 33 interrupt-parent = <&GIC>;
68 GIC: interrupt-controller@01c81000 {
72 interrupt-controller;
73 #interrupt-cells = <1>;
95 interrupt-parent = < &GIC >;
111 interrupt-parent = <&GIC>;
121 interrupt-parent = <&GIC>;
130 interrupt-parent = <&GIC>;
138 interrupt-parent = <&GIC>;
151 interrupt-parent = <&GIC>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | icon.dts | 52 UIC0: interrupt-controller0 {
54 interrupt-controller;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
64 interrupt-controller;
69 #interrupt-cells = <2>;
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
76 interrupt-controller;
81 #interrupt-cells = <2>;
[all …]
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| H A D | rainier.dts | 57 UIC0: interrupt-controller0 {
59 interrupt-controller;
64 #interrupt-cells = <2>;
67 UIC1: interrupt-controller1 {
69 interrupt-controller;
74 #interrupt-cells = <2>;
76 interrupt-parent = <&UIC0>;
79 UIC2: interrupt-controller2 {
81 interrupt-controller;
86 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/samsung/ |
| H A D | exynos3250-pinctrl.dtsi | 34 interrupt-controller;
35 #interrupt-cells = <2>;
42 interrupt-controller;
43 #interrupt-cells = <2>;
50 interrupt-controller;
51 #interrupt-cells = <2>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
66 interrupt-controller;
67 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/nintendo/ |
| H A D | wii.txt | 32 - interrupts : should contain the VI interrupt
44 1.b.i) The "Flipper" interrupt controller node
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
47 The node for the "Flipper" interrupt controller must be placed under
52 - #interrupt-cells : <1>
54 - interrupt-controller
65 - interrupts : should contain the DSP interrupt
77 - interrupts : should contain the SI interrupt
88 - interrupts : should contain the AI interrupt
98 - interrupts : should contain the EXI interrupt
[all...] |
| /freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
| H A D | exynos7885-pinctrl.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-controller;
21 #interrupt-cells = <2>;
28 interrupt-controller;
29 #interrupt-cells = <2>;
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 interrupt-parent = <&gic>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/riscv/sifive/ |
| H A D | fu540-c000.dtsi | 37 cpu0_intc: interrupt-controller {
38 #interrupt-cells = <1>;
40 interrupt-controller;
64 cpu1_intc: interrupt-controller {
65 #interrupt-cells = <1>;
67 interrupt-controller;
91 cpu2_intc: interrupt-controller {
92 #interrupt-cells = <1>;
94 interrupt-controller;
118 cpu3_intc: interrupt
[all...] |