xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/actions,owl-sirq.yaml (revision fac71e4e09885bb2afa3d984a0c239a52e1a7418) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Actions Semi Owl SoCs SIRQ interrupt controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
12
13description: |
14  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
15  and S900) and provides support for handling up to 3 external interrupt lines.
16
17properties:
18  compatible:
19    enum:
20      - actions,s500-sirq
21      - actions,s700-sirq
22      - actions,s900-sirq
23
24  reg:
25    maxItems: 1
26
27  interrupt-controller: true
28
29  '#interrupt-cells':
30    const: 2
31    description:
32      The first cell is the input IRQ number, between 0 and 2, while the second
33      cell is the trigger type as defined in interrupt.txt in this directory.
34
35  interrupts:
36    description: |
37      Contains the GIC SPI IRQs mapped to the external interrupt lines.
38      They shall be specified sequentially from output 0 to 2.
39    minItems: 3
40    maxItems: 3
41
42required:
43  - compatible
44  - reg
45  - interrupt-controller
46  - '#interrupt-cells'
47  - interrupts
48
49additionalProperties: false
50
51examples:
52  - |
53    #include <dt-bindings/interrupt-controller/arm-gic.h>
54
55    sirq: interrupt-controller@b01b0200 {
56      compatible = "actions,s500-sirq";
57      reg = <0xb01b0200 0x4>;
58      interrupt-controller;
59      #interrupt-cells = <2>;
60      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
61                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
62                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
63    };
64
65...
66