| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
18 mapping of the PCIe interface to interrupt numbers
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| H A D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
20 # for the first generation of PAXB based controller, used in SoCs
22 - brcm,iproc-pcie
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| H A D | rockchip-dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
22 - description: AHB clock for PCIe master
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| H A D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
17 snps,dw-pcie.yaml.
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| H A D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
21 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
22 interrupt-cells: should be set to 1
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | marvell-bt-8xxx.txt | 1 Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based)
2 ------
9 - compatible : should be one of the following:
10 * "marvell,sd8897-bt" (for SDIO)
11 * "marvell,sd8997-bt" (for SDIO)
16 - marvell,cal-data: Calibration data downloaded to the device during
20 - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
22 - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host
25 - interrupt-names: Used only for USB based devices (See below)
26 - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the
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| H A D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
18 - interrupts: Should contain the TSE interrupts and its mode.
19 - interrupt-names: Should contain the interrupt names
20 "rx_irq": xDMA Rx dispatcher interrupt
21 "tx_irq": xDMA Tx dispatcher interrupt
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| H A D | microchip,sparx5-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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| H A D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| H A D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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| /freebsd/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-mpc.txt | 5 - reg : Offset and length of the register set for the device
6 - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
9 "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
13 - interrupts : <a b> where a is the interrupt number and b is a
15 information for the interrupt. This should be encoded based on
16 the information in section 2) depending on the type of interrupt
18 - fsl,preserve-clocking : boolean; if defined, the clock settings
20 - clock-frequency : desired I2C bus clock frequency in Hz.
21 - fsl,timeout : I2C bus timeout in microseconds.
25 /* MPC5121 based board */
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | realtek-smi.txt | 1 Realtek SMI-based Switches
4 The SMI "Simple Management Interface" is a two-wire protocol using
5 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
7 SMI-based Realtek devices.
11 - compatible: must be exactly one of:
23 - mdc-gpios: GPIO line for the MDC clock line.
24 - mdio-gpios: GPIO line for the MDIO data line.
25 - reset-gpios: GPIO line for the reset signal.
28 - realtek,disable-leds: if the LED drivers are not used in the
34 - interrupt-controller
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| /freebsd/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | qcom,ath10k.txt | 4 - compatible: Should be one of the following:
6 * "qcom,ipq4019-wifi"
7 * "qcom,wcn3990-wifi"
9 PCI based devices uses compatible string "qcom,ath10k" and takes calibration
10 data along with board specific data via "qcom,ath10k-calibration-data".
11 Rest of the properties are not applicable for PCI based devices.
13 AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
15 "qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
18 In general, entry "qcom,ath10k-pre-calibration-data" and
19 "qcom,ath10k-calibration-data" conflict with each other and only one
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | twl-family.txt | 10 - compatible : Must be "ti,twl4030";
11 For Integrated power-management/audio CODEC device used in OMAP3
12 based boards
13 - compatible : Must be "ti,twl6030";
14 For Integrated power-management used in OMAP4 based boards
15 - interrupts : This i2c device has an IRQ line connected to the main SoC
16 - interrupt-controller : Since the twl support several interrupts internally,
17 it is considered as an interrupt controller cascaded to the SoC one.
18 - #interrupt-cells = <1>;
21 - Child nodes contain in the twl. The twl family is made of several variants
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| H A D | gateworks-gsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Watchdog Timer
15 - GPIO
16 - Pushbutton controller
17 - Hardware monitor with ADC's for temperature and voltage rails and
21 - Tim Harvey <tharvey@gateworks.com>
25 pattern: "gsc@[0-9a-f]{1,2}"
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| /freebsd/share/man/man4/ |
| H A D | ath.4 | 1 .\"-
2 .\" Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
39 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
55 driver provides support for wireless network adapters based on
61 IBSS, MBSS, WDS/DWDS TDMA, and host-based access point operation modes.
70 AR5210-based devices support 802.11a operation with transmit speeds
72 AR5211-based devices support 802.11a and 802.11b operation with transmit
75 AR5212-based devices support 802.11a, 802.11b, and 802.11g operation
83 only interoperable with other Atheros-based devices.)
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| H A D | re.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
55 driver provides support for various NICs based on the RealTek RTL8139C+,
59 NICs based on the 8139C+ and 810xE are capable of 10 and 100Mbps speeds
61 NICs based on the 8169, 816xS, 811xS, 8168 and 8111 are capable of 10, 100
67 features, and use a descriptor-based DMA mechanism.
71 The 8139C+ is a single-chip solution combining both a 10/100 MAC and PHY.
73 The 816xS, 811xS, 8168 and 8111 are single-chip devices containing both a
76 in both 32-bit PCI and 64-bit PCI models.
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| /freebsd/sys/contrib/device-tree/Bindings/power/supply/ |
| H A D | bq24257.txt | 1 Binding for TI bq24250/bq24251/bq24257 Li-Ion Charger
4 - compatible: Should contain one of the following:
8 - reg: integer, i2c address of the device.
9 - interrupts: Interrupt mapping for GPIO IRQ (configure for both edges). Use in
10 conjunction with "interrupt-parent".
11 - ti,battery-regulation-voltage: integer, maximum charging voltage in uV.
12 - ti,charge-current: integer, maximum charging current in uA.
13 - ti,termination-current: integer, charge will be terminated when current in
14 constant-voltage phase drops below this value (in uA).
17 - pg-gpios: GPIO used for connecting the bq2425x device PG (Power Good) pin.
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| H A D | bq24257.yaml | 1 # SPDX-License-Identifier: GPL-2.0
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Bq24250, bq24251 and bq24257 Li-Ion Charger
11 - Sebastian Reichel <sre@kernel.org>
14 - $ref: power-supply.yaml#
19 - ti,bq24250
20 - ti,bq24251
21 - ti,bq24257
29 ti,battery-regulation-voltage:
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | brcm,bcm7271-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom 8250 based serial port
10 - Al Cooper <alcooperx@gmail.com>
13 - $ref: serial.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
23 - enum:
24 - brcm,bcm7271-uart
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| /freebsd/sys/contrib/device-tree/Bindings/net/nfc/ |
| H A D | nfcmrvl.txt | 4 - compatible: Should be:
5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
6 - "marvell,nfc-i2c" for I2C devices
7 - "marvell,nfc-spi" for SPI devices
10 - pinctrl-names: Contains only one value - "default".
11 - pintctrl-0: Specifies the pin control groups used for this controller.
12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
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| /freebsd/sys/contrib/device-tree/Bindings/arm/freescale/ |
| H A D | fsl,scu.txt | 2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
26 include "gip3" if want to support general MU interrupt.
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
28 rx, and 1 optional MU channel for general interrupt.
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| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | writing-bindings.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 Documentation/devicetree/bindings/submitting-patches.rst
17 - DO attempt to make bindings complete even if a driver doesn't support some
18 features. For example, if a device has an interrupt, then include the
21 - DON'T refer to Linux or "device driver" in bindings. Bindings should be
22 based on what the hardware has, not what an OS and driver currently support.
24 - DO use node names matching the class of the device. Many standard names are
27 - DO check that the example matches the documentation especially after making
30 - DON'T create nodes just for the sake of instantiating drivers. Multi-function
34 - DON'T use 'syscon' alone without a specific compatible string. A 'syscon'
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
8 based SoCs
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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| /freebsd/lib/libpmc/ |
| H A D | pmc.soft.3 | 29 .Nd measurements using software based events
37 16 sampling counters using software events based on various sources.
39 .Bl -column "PMC_CAP_INTERRUPT" "Support"
57 .Bl -tag -width indent
65 Interrupt filter executed
67 Interrupt filter returned FILTER_HANDLED.
69 Interrupt filter returned FILTER_SCHEDULE_ITHREAD.
73 Interrupt filter returned FILTER_STRAY.
105 .An -nosplit
|