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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm's USB HS PHY
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 if:
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
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H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
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H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
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H A Dnvidia,tegra20-usb-phy.txt1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
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H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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H A Drenesas,rcar-gen2-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
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H A Drcar-gen2-phy.txt1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
4 2 USB PHY contains.
7 - compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC.
8 "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
9 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
10 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
11 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
12 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
13 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drenesas,rcar-usb2-clock-sel.txt1 * Renesas R-Car USB 2.0 clock selector
3 This file provides information on what the device node for the R-Car USB 2.0
6 If you connect an external clock to the USB_EXTAL pin only, you should set
8 If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
12 Case 1: An external clock connects to R-Car SoC
13 +----------+ +--- R-Car ---------------------+
14 |External |---|USB_EXTAL ---> all usb channels|
16 +----------+ +-------------------------------+
19 Case 2: An oscillator connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
[all …]
H A Drenesas,rcar-usb2-clock-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car USB 2.0 clock selector
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 If you connect an external clock to the USB_EXTAL pin only, you should set
15 If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
19 Case 1: An external clock connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
[all …]
/freebsd/sys/contrib/device-tree/Bindings/connector/
H A Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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H A Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
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H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
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H A Dci-hdrc-usb2.txt1 * USB2 ChipIdea USB controller for ci13xxx
4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
[all …]
H A Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
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H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
4 as described in 'usb/generic.txt'
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
[all …]
H A Dehci-omap.txt1 OMAP HS USB EHCI controller
3 This device is usually the child of the omap-usb-host
4 Documentation/devicetree/bindings/mfd/omap-usb-host.txt
8 - compatible: should be "ti,ehci-omap"
9 - reg: should contain one register range i.e. start and length
10 - interrupts: description of the interrupt line
14 - phys: list of phandles to PHY nodes.
15 This property is required if at least one of the ports are in
19 Documentation/devicetree/bindings/mfd/omap-usb-host.txt
24 compatible = "ti,ehci-omap";
H A Ddwc3-xilinx.txt1 Xilinx SuperSpeed DWC3 USB SoC controller
4 - compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
5 - reg: Base address and length of the register control block
6 - clocks: A list of phandles for the clocks listed in clock-names
7 - clock-names: Should contain the following:
9 operation and >= 60MHz for HS operation
12 - resets: A list of phandles for resets listed in reset-names
13 - reset-names:
14 "usb_crst" USB core reset
15 "usb_hibrst" USB hibernation reset
[all …]
H A Dmicrochip,usb5744.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/microchip,usb5744.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB5744 4-port Hub Controller
10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
11 low power, low pin count configurable and fully compliant with the USB 3.1
13 (LS) USB signaling, offering complete coverage of all defined USB operating
14 speeds. The new SuperSpeed hubs operate in parallel with the USB 2.0
16 USB 2.0 traffic.
[all …]
H A Drenesas,usbhs.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/usb/renesas,usbhs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas USBHS (HS-USB) controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - const: renesas,usbhs-r7s72100 # RZ/A1
17 - const: renesas,rza1-usbhs
19 - items:
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H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
[all …]
H A Drenesas,usb3-peri.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/usb/renesas,usb3-peri.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas USB 3.0 Peripheral controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - enum:
17 - renesas,r8a774a1-usb3-peri # RZ/G2M
18 - renesas,r8a774b1-usb3-peri # RZ/G2N
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-so
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/freebsd/sys/arm/qualcomm/
H A Dipq4018_usb_hs_phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 {"qcom,usb-hs-ipq4019-phy", 1},
77 * For power-off - assert por, sleep for 10ms, assert srif, in ipq4018_usb_hs_phynode_phy_enable()
80 rv = hwreset_assert(sc->por_rst); in ipq4018_usb_hs_phynode_phy_enable()
81 if (rv != 0) in ipq4018_usb_hs_phynode_phy_enable()
84 rv = hwreset_assert(sc->srif_rst); in ipq4018_usb_hs_phynode_phy_enable()
85 if (rv != 0) in ipq4018_usb_hs_phynode_phy_enable()
90 * For power-on - power off first, then deassert srif, then in ipq4018_usb_hs_phynode_phy_enable()
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