Lines Matching +full:hs +full:- +full:usb +full:- +full:if

1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6  - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7    For Tegra30, must contain "nvidia,tegra30-usb-phy".  Otherwise, must contain
8    "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10  - reg : Defines the following set of registers, in the order listed:
11    - The PHY's own register set.
13    - The register set of the PHY containing the UTMI pad control registers.
14      Present if-and-only-if phy_type == utmi.
15  - phy_type : Should be one of "utmi", "ulpi" or "hsic".
16  - clocks : Defines the clocks listed in the clock-names property.
17  - clock-names : The following clock names must be present:
18    - reg: The clock needed to access the PHY's own registers. This is the
20    - pll_u: PLL_U. Always present.
21    - timer: The timeout clock (clk_m). Present if phy_type == utmi.
22    - utmi-pads: The clock needed to access the UTMI pad control registers.
23      Present if phy_type == utmi.
24    - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
27      Present if phy_type == ulpi, and ULPI link mode is in use.
28  - resets : Must contain an entry for each entry in reset-names.
30  - reset-names : Must include the following entries:
31    - usb: The PHY's own reset signal.
32    - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
33      registers. Required even if phy_type == ulpi.
36   - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
39   - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
41   - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
42   - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
44   - nvidia,term-range-adj : Range adjusment on terminations
45   - Either one of the following for HS driver output control:
46     - nvidia,xcvr-setup : integer, uses the provided value.
47     - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
48       from the on-chip fuses
49     If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
50   - nvidia,xcvr-lsfslew : LS falling slew rate control.
51   - nvidia,xcvr-lsrslew :  LS rising slew rate control.
54   - nvidia,xcvr-hsslew : HS slew rate control.
55   - nvidia,hssquelch-level : HS squelch detector level.
56   - nvidia,hsdiscon-level : HS disconnect detector level.
59   - nvidia,has-legacy-mode : boolean indicates whether this controller can
62     the USB controller.
63   - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
65   - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
66     "host", "peripheral", or "otg". Defaults to "host" if not defined.
70   - nvidia,has-utmi-pad-registers : boolean indicates whether this controller
71     contains the UTMI pad control registers common to all USB controllers.
74   - vbus-supply: regulator for VBUS