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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Df16cintrin.h1 /*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
47 /// half-precision float value.
58 /// A 32-bit single-precision float value to be converted to a 16-bit
[all …]
H A Davxneconvertintrin.h1 /*===-------------- avxneconvertintrin.h - AVXNECONVERT --------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
61 /// Convert scalar BF16 (16-bit) floating-point element
63 /// single-precision (32-bit) floating-point, broadcast it to packed
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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsWebAssembly.def1 // BuiltinsWebAssembly.def - WebAssembly builtin function database -*- C++ -*-//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file defines the WebAssembly-specific builtin function database.
14 //===----------------------------------------------------------------------===//
28 // Thread-local storage
29 TARGET_BUILTIN(__builtin_wasm_tls_size, "z", "nc", "bulk-memory")
30 TARGET_BUILTIN(__builtin_wasm_tls_align, "z", "nc", "bulk-memory")
31 TARGET_BUILTIN(__builtin_wasm_tls_base, "v*", "nU", "bulk-memory")
40 TARGET_BUILTIN(__builtin_wasm_throw, "vIUiv*", "r", "exception-handling")
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/freebsd/contrib/libcbor/src/cbor/
H A Dfloats_ctrls.h2 * Copyright (c) 2014-2020 Pavel Kalvoda <me@pavelkalvoda.com>
40 /** Get a half precision float
44 * @param item A half precision float
45 * @return half precision value
50 /** Get a single precision float
54 * @param item A single precision float
55 * @return single precision value
60 /** Get a double precision float
64 * @param item A double precision float
65 * @return double precision value
[all …]
H A Dencoding.h2 * Copyright (c) 2014-2020 Pavel Kalvoda <me@pavelkalvoda.com>
20 * - a logical `value` to encode (except for trivial items such as NULLs)
21 * - an output `buffer` pointer
22 * - a `buffer_size` specification
101 /** Encodes a half-precision float
103 * Since there is no native representation or semantics for half floats
104 * in the language, we use single-precision floats, as every value that
105 * can be expressed as a half-float can also be expressed as a float.
109 * - Infinity, NaN are preserved
110 * - Zero is preserved
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // RISC-V subtarget features and instruction predicates.
11 //===----------------------------------------------------------------------===//
13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V
16 // name - Name of the extension in lower case.
17 // major - Major version of extension.
18 // minor - Minor version of extension.
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/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Dsinh_3u.c2 * Double-precision sinh(x) function.
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
14 #define Half 0x3fe0000000000000 macro
18 /* Approximation for double-precision sinh(x) using expm1.
19 sinh(x) = (exp(x) - exp(-x)) / 2.
21 __v_sinh(0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
22 want 0x1.ab34e59d678d9p-2. */
30 double halfsign = asdouble (Half | sign); in sinh()
39 double-precision exp helper. For large x sinh(x) is dominated in sinh()
[all …]
H A Dsinhf_2u3.c2 * Single-precision sinh(x) function.
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
14 #define Half 0x3f000000 macro
20 /* Approximation for single-precision sinh(x) using expm1.
21 sinh(x) = (exp(x) - exp(-x)) / 2.
23 sinhf(0x1.e34a9ep-4) got 0x1.e469ep-4 want 0x1.e469e4p-4. */
31 float halfsign = asfloat (Half | sign); in sinhf()
45 double-precision exp helper. For large x sinh(x) dominated by exp(x), in sinhf()
50 ~= (exp(|x| / 2)) ^ 2 / -2 for x < 0. in sinhf()
[all …]
H A Datanh_3u.c2 * Double-precision atanh(x) function.
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
14 #define Half 0x3fe0000000000000 macro
16 #define Ln2Hi 0x1.62e42fefa3800p-1
17 #define Ln2Lo 0x1.ef35793c76730p-45
19 0x00095f62 /* top32(asuint64(1)) - top32(asuint64(sqrt(2)/2)). */
27 /* Helper for calculating log(1 + x) using order-18 polynomial on a reduced in log1p_inline()
28 interval. Copied from log1p_2u.c, with no special-case handling. See that in log1p_inline()
36 int32_t k = (int32_t) (u >> 20) - OneTop12; in log1p_inline()
[all …]
H A Datanhf_3u1.c2 * Single-precision atanh(x) function.
4 * Copyright (c) 2022-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
14 #define Half 0x3f000000 macro
17 #define Ln2 0x1.62e43p-1f
18 /* asuint(0x1p-12), below which atanhf(x) rounds to x. */
26 /* Approximate log(1+m) on [-0.25, 0.5] using Estrin scheme. */ in eval_poly()
47 special-case handling. See that file for details of the algorithm. */ in log1pf_inline()
49 int k = (asuint (m) - 0x3f400000) & 0xff800000; in log1pf_inline()
50 float s = asfloat (Four - k); in log1pf_inline()
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/freebsd/lib/libpmc/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json129 "PublicDescription": "Attributable Level 1 data cache write-back",
132 "BriefDescription": "Attributable Level 1 data cache write-back"
147 "PublicDescription": "Attributable Level 2 data cache write-back",
150 "BriefDescription": "Attributable Level 2 data cache write-back"
273 "PublicDescription": "Access to another socket in a multi-socket system",
276 "BriefDescription": "Access to another socket in a multi-socket system"
303 … "PublicDescription": "Attributable memory read access to another socket in a multi-socket system",
306 … "BriefDescription": "Attributable memory read access to another socket in a multi-socket system"
309 …"PublicDescription": "Level 1 data cache long-latency read miss. The counter counts each memory r…
312 "BriefDescription": "Level 1 data cache long-latency read miss"
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/
H A Dfp_div_impl.inc1 //===-- fp_div_impl.inc - Floating point division -----------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements soft-float division with the IEEE-754 default
12 //===----------------------------------------------------------------------===//
16 // The __divXf3__ function implements Newton-Raphson floating point division.
19 // every iteration, the two modes are supported: N full-width iterations (as
20 // it is done for float32 by default) and (N-1) half-width iteration plus one
21 // final full-width iteration. It is expected that half-width integer
26 // Half the bit-size of rep_t
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/freebsd/lib/msun/man/
H A Dieee.333 .Nd IEEE standard 754 for floating-point arithmetic
35 The IEEE Standard 754 for Binary Floating-Point Arithmetic
36 defines representations of floating-point numbers and abstract
37 properties of arithmetic operations relating to precision,
39 .Ss IEEE STANDARD 754 Floating-Point Arithmetic
43 .Bd -ragged -offset indent -compact
49 Zero is represented ambiguously as +0 or \-0.
50 .Bd -ragged -offset indent -compact
53 with like signs; but x\-x yields +0 for every
57 .Fn copysign x \(+-0 .
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H A Dsinpi.332 .Nd half\(encycle sine functions
51 and measure angles in half-cycles.
60 If \*(Bax\*(Ba \*(Ge 2^(p - 1)
61 where p is the floating\(enpoint precision of
65 .Bl -tag -width "sinpi(NaN)"
85 The half\(encycle trignometric functions were written by
90 \(dqIEEE Standard for Floating-Point Arithmetic\(dq
92 ISO/IEC TS 18661-4 ,
H A Dtanpi.332 .Nd half\(encycle tangent functions
51 and measure angles in half-cycles.
60 If \*(Bax\*(Ba \*(Ge 2^(p - 1)
61 where p is the floating\(enpoint precision of
65 .Bl -tag -width "tanpi(+n/2)"
87 The half\(encycle trignometric functions were written by
92 \(dqIEEE Standard for Floating-Point Arithmetic\(dq
94 ISO/IEC TS 18661-4 ,
H A Dcospi.332 .Nd half\(encycle cosine functions
51 and measure angles in half-cycles.
60 If \*(Bax\*(Ba \*(Ge 2^(p - 1)
61 where p is the floating\(enpoint precision of
65 .Bl -tag -width "cospi(+n/2)"
75 returns \-1 for odd integers
91 The half\(encycle trignometric functions were written by
96 \(dqIEEE Standard for Floating-Point Arithmetic\(dq
98 ISO/IEC TS 18661-4 ,
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DWebAssembly.cpp1 //===--- WebAssembly.cpp - Implement WebAssembly target feature support ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
34 {"mvp"}, {"bleeding-edge"}, {"generic"}};
39 if (Name != "mvp" && Name != "experimental-mv") in setABI()
49 .Case("bulk-memory", HasBulkMemory) in hasFeature()
50 .Case("exception-handling", HasExceptionHandling) in hasFeature()
51 .Case("extended-const", HasExtendedConst) in hasFeature()
52 .Case("half-precision", HasHalfPrecision) in hasFeature()
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/freebsd/contrib/arm-optimized-routines/math/aarch64/sve/
H A Datanhf.c2 * Single-precision vector atanh(x) function.
4 * Copyright (c) 2023-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
15 #define Half (0x3f000000) macro
26 /* Approximation for vector single-precision atanh(x) using modified log1p.
28 _ZGVsMxv_atanhf(0x1.f1583p-5) got 0x1.f1f4fap-5
29 want 0x1.f1f4f6p-5. */
35 svfloat32_t halfsign = svreinterpret_f32 (svorr_x (pg, sign, Half)); in SV_NAME_F1()
39 * (1+x)/(1-x) = 1 + 2x/(1-x). */ in SV_NAME_F1()
42 /* ln((1+x)/(1-x)) = ln(1+2x/(1-x)) = ln(1 + y). */ in SV_NAME_F1()
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H A Datanh.c2 * Double-precision SVE atanh(x) function.
4 * Copyright (c) 2023-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
16 #define Half (0x3fe0000000000000) macro
24 /* SVE approximation for double-precision atanh, based on log1p.
26 _ZGVsMxv_atanh(0x1.ffae6288b601p-6) got 0x1.ffd8ff31b5019p-6
27 want 0x1.ffd8ff31b501cp-6. */
34 svfloat64_t halfsign = svreinterpret_f64 (svorr_x (pg, sign, Half)); in SV_NAME_D1()
40 (1+x)/(1-x) = 1 + 2x/(1-x). */ in SV_NAME_D1()
44 /* ln((1+x)/(1-x)) = ln(1+2x/(1-x)) = ln(1 + y). */ in SV_NAME_D1()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td1 //===----------------------------------------------------------------------===//
6 def ModeThumb : SubtargetFeature<"thumb-mode", "IsThumb",
10 def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
14 //===----------------------------------------------------------------------===//
21 string TargetFeatureName, // String used for -target-feature.
32 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
37 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
38 // extension) and MVE (even in the integer-only version).
40 "Enable 16-bit FP registers",
44 "Enable 64-bit FP registers",
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/freebsd/contrib/arm-optimized-routines/math/aarch64/
H A Dsincospi_4u.c2 * Double-precision scalar sincospi function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
16 C2_hi = 4, C2_lo = C2 - C2_hi (~=1.16771278)
24 .poly = { 0x1.921fb54442d184p1, -0x1.2aef39896f94bp0, 0x1.466bc6775ab16p1,
25 -0x1.32d2cce62dc33p-1, 0x1.507834891188ep-4, -0x1.e30750a28c88ep-8,
26 0x1.e8f48308acda4p-12, -0x1.6fc0032b3c29fp-16,
27 0x1.af86ae521260bp-21, -0x1.012a9870eeb7dp-25 },
38 -1 or +1 if iy represents half an integer
39 -1 if round(y) is odd.
41 -2 or +2 if iy represents and integer.
[all …]
H A Dsincospif_3u2.c2 * Single-precision scalar sincospi function.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
19 .poly = { 0x1.921fb6p1f, -0x1.4abbcep2f, 0x1.466bc6p1f, -0x1.32d2ccp-1f,
20 0x1.50783p-4f, -0x1.e30750p-8f },
31 -1 or +1 if iy represents half an integer
32 -1 if round(y) is odd.
34 -2 or +2 if iy represents and integer.
35 -2 if iy is odd.
37 The argument is the bit representation of a positive non-zero
38 finite floating-point value which is either a half or an integer. */
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Dfloating-point.json65 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
71 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
76 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
82 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
87 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
93 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
98 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
104 …-bit packed single precision floating-point instructions retired; some instructions will count twi…
109 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
115 …-bit packed double precision floating-point instructions retired; some instructions will count twi…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
[all …]
/freebsd/contrib/libcbor/doc/source/api/
H A Dtype_7.rst4 This type combines two completely unrelated types of items -- floating point numbers and special va…
65 Half floats
67 CBOR supports two `bytes wide ("half-precision") <https://en.wikipedia.org/wiki/Half-precision_floa…
68 … :func:`cbor_encode_half`, which will handle any values that cannot be represented as a half-float.

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