Searched full:gen12 (Results 1 – 15 of 15) sorted by relevance
92 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer93 * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.096 * @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer99 * @MEI_ME_PCH12_SPS_ITOUCH_CFG: Platform Controller Hub Gen12
95 /* Gen12 OAR unit */103 /* Gen12 OAG unit */137 /* Gen12 OAM unit */
84 /* gen12 */
13 /* GEN8 to GEN12 Reg State Context */76 /* in Gen12 ID 0x7FF is reserved to indicate idle */
123 #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */291 #define PIPE_CONTROL_AMFS_FLUSH (1<<25) /* gen12+ */310 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
42 * For pre-gen12 platforms pat_index is the same as enum in gen8_pte_encode()1023 * Gen12 has inherited the same read-only fault issue from gen11. in gen8_ppgtt_create()
522 * Mid-thread pre-emption is not available in Gen12. Unfortunately, in intel_engine_setup()733 * In Gen12, Even numbered physical instance always are connected in gen11_vdbox_has_sfc()1751 * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
15 /* GuC RC is unavailable for pre-Gen12 */ in __guc_rc_supported()
2778 /* Gen12+ */ in xe_oa_init_supported_formats()2819 /* Support OA only with GuC submission and Gen12+ */ in xe_oa_init()
452 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ in disable_all_event_handlers()
503 * HDCP register access for gen12+ need the transcoder associated.
92 * On top of PSR2, GEN12 adds a intermediate power savings state that turns3776 * But GEN12 supports a instance of PSR registers per transcoder. in intel_psr_init()
1305 /* prior GEN12 only have one EDP PSR */ in gen8_de_misc_irq_handler()
1009 * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.3247 * whether a subslice is available. Starting with Gen12 we use the