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Searched +full:gcc +full:- +full:ipq5332 (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5332-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
10 - Bjorn Andersson <andersson@kernel.org>
14 domains on IPQ5332 and IPQ5424.
17 include/dt-bindings/clock/qcom,gcc-ipq5332.h
18 include/dt-bindings/clock/qcom,gcc-ipq5424.h
23 - qcom,ipq5332-gcc
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,ipq5332-uniphy-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nitheesh Sekar <quic_nsekar@quicinc.com>
11 - Varadarajan Narayanan <quic_varada@quicinc.com>
14 PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs
19 - qcom,ipq5018-uniphy-pcie-phy
20 - qcom,ipq5332-uniphy-pcie-phy
33 "#phy-cells":
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H A Dqcom,ipq5332-usb-hsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sricharan Ramabadhran <quic_srichara@quicinc.com>
11 - Varadarajan Narayanan <quic_varada@quicinc.com>
15 IPQ5018, IPQ5332 SoCs.
20 - enum:
21 - qcom,ipq5018-usb-hsphy
22 - qcom,ipq5332-usb-hsphy
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/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
12 # Use the combined qcom,snps-dwc3 instead
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
28 - qcom,ipq5018-dwc3
29 - qcom,ipq5332-dwc3
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H A Dqcom,snps-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wesley Cheng <quic_wcheng@quicinc.com>
19 const: qcom,snps-dwc3
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
28 - qcom,ipq5018-dwc3
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml#
19 - enum:
20 - qcom,apq8064-qfprom
21 - qcom,apq8084-qfprom
22 - qcom,ipq5018-qfprom
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom,apcs-kpss-global.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Jassi Brar <jassisinghbrar@gmail.com>
19 - items:
20 - enum:
21 - qcom,ipq5018-apcs-apps-global
22 - qcom,ipq5332-apcs-apps-global
23 - qcom,ipq5424-apcs-apps-global
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/linux/drivers/clk/qcom/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
242 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
243 the output clocks to the networking hardware and GCC blocks.
263 tristate "IPQ5332 Global Clock Controller"
266 Support for the global clock controller on ipq5332 devices.
1411 Say Y if you want to toggle LPASS-adjacent resets within
1529 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1531 Support for the high-frequency PLLs present on Qualcomm devices.
1538 Support for the Krait ACC and GCC clock controllers. Say Y
H A Dgcc-ipq5332.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/interconnect-provider.h>
13 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
14 #include <dt-bindings/interconnect/qcom,ipq5332.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-uniphy-pcie-28lp.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
143 const struct qcom_uniphy_pcie_data *data = phy->data; in qcom_uniphy_pcie_init()
145 void __iomem *base = phy->base; in qcom_uniphy_pcie_init()
148 for (lane = 0; lane < phy->lanes; lane++) { in qcom_uniphy_pcie_init()
149 init_seq = data->init_seq; in qcom_uniphy_pcie_init()
151 for (i = 0; i < data->init_seq_num; i++) in qcom_uniphy_pcie_init()
154 base += data->lane_offset; in qcom_uniphy_pcie_init()
162 clk_bulk_disable_unprepare(phy->num_clks, phy->clks); in qcom_uniphy_pcie_power_off()
164 return reset_control_assert(phy->resets); in qcom_uniphy_pcie_power_off()
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/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - enum:
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq5018
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/linux/drivers/thermal/qcom/
H A Dtsens.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/nvmem-consumer.h>
26 * struct tsens_irq_data - IRQ status and temperature violations
81 if (priv->num_sensors > MAX_SENSORS) in tsens_read_calibration()
82 return -EINVAL; in tsens_read_calibration()
88 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); in tsens_read_calibration()
89 if (ret == -ENOENT) in tsens_read_calibration()
90 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); in tsens_read_calibration()
94 dev_dbg(priv->dev, "calibration mode is %d\n", mode); in tsens_read_calibration()
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); in tsens_read_calibration()
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