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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dgate.txt1 Binding for Texas Instruments gate clock.
3 This binding uses the common clock binding[1]. This clock is
4 quite much similar to the basic gate-clock [2], however,
6 is provided for this clock, the code assumes that a clockdomain
7 will be controlled instead and the corresponding hw-ops for
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
12 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
15 - compatible : shall be one of:
16 "ti,gate-clock" - basic gate clock
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
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H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cell
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsprd,sc9860-clk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 clock
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
17 - sprd,sc9860-agcp-gate
18 - sprd,sc9860-aonsecure-clk
[all …]
H A Dsprd,sc9860-clk.txt1 Spreadtrum SC9860 Clock Binding
2 ------------------------
5 - compatible: should contain the following compatible strings:
6 - "sprd,sc9860-pmu-gate"
7 - "sprd,sc9860-pll"
8 - "sprd,sc9860-ap-clk"
9 - "sprd,sc9860-aon-prediv"
10 - "sprd,sc9860-apahb-gate"
11 - "sprd,sc9860-aon-gate"
12 - "sprd,sc9860-aonsecure-clk"
[all …]
H A Dsprd,ums512-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: UMS512 Soc clock controller
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - sprd,ums512-apahb-gate
19 - sprd,ums512-ap-clk
[all …]
H A Dsprd,sc9863a-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/spr
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H A Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
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H A Dam35xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "ti,am35xx-gate-clock";
13 ti,bit-shift = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,gate-clock";
21 ti,bit-shift = <9>;
25 #clock-cells = <0>;
26 compatible = "ti,am35xx-gate-clock";
[all …]
H A Domap3430es1-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3430 ES1 clock data
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
22 ti,index-starts-at-one;
26 #clock-cells = <0>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2430 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
[all …]
H A Domap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,omap3-dpll-per-j-type-clock";
16 #clock-cells = <0>;
17 compatible = "ti,hsdiv-gate-clock";
19 ti,bit-shift = <0x1e>;
21 ti,set-rate-parent;
22 ti,set-bit-to-disable;
26 #clock-cells = <0>;
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * @defgroup clock_ids Clock Identifiers
235 * @defgroup nafll_clks NAFLL clock sources
350 /** @brief output of gate CLK_ENB_FUSE */
354 * @details output of gate CLK_ENB_GPU. This output connects to the GPU
355 * pwrclk. @warning: This is almost certainly not the clock you think
356 * it is. If you're looking for the clock of the graphics engine, see
360 /** @brief output of gate CLK_ENB_PCIE */
364 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
366 /** @brief output of gate CLK_ENB_PCIERX0*/
[all …]
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
9 * @defgroup bpmp_clock_ids Clock ID's
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
58 /** @brief clock recovered from EAVB input */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_hdmi.txt1 Device-Tree bindings for drm hdmi driver
4 - compatible: value should be one among the following:
5 1) "samsung,exynos4210-hdmi"
6 2) "samsung,exynos4212-hdmi"
7 3) "samsung,exynos5420-hdmi"
8 4) "samsung,exynos5433-hdmi"
9 - reg: physical base address of the hdmi and length of memory mapped
11 - interrupts: interrupt number to the cpu.
12 - hpd-gpios: following information about the hotplug gpio pin.
16 - ddc: phandle to the hdmi ddc node
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dsharkl3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 compatible = "simple-bus";
15 #address-cells = <2>;
16 #size-cells = <2>;
20 compatible = "sprd,sc9863a-glbregs", "syscon",
21 "simple-mfd";
23 #address-cells = <1>;
[all …]
H A Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
[all …]
/freebsd/sys/arm/mv/clk/
H A Dperiph.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
92 .clk_def.full_dd.gate.clkdef.name = _name, \
93 .clk_def.full_dd.gate.offset = CLK_DIS, \
94 .clk_def.full_dd.gate.shift = _gate_shift, \
95 .clk_def.full_dd.gate.on_value = 0, \
96 .clk_def.full_dd.gate.off_value = 1, \
97 .clk_def.full_dd.gate.mask = 0x1, \
98 .clk_def.full_dd.gate.gate_flags = 0x0 \
126 .clk_def.full_d.gate.clkdef.name = _name, \
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbi
[all...]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drockchip-dwmac.txt6 - compatible: should be "rockchip,<name>-gamc"
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
[all …]

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