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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm283x-rpi-usb-otg.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
8 * fifo sizes shouldn't exceed 3776 bytes.
10 g-tx-fifo-size = <256 256 512 512 512 768 768>;
H A Dbcm283x-rpi-usb-peripheral.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
6 g-tx-fifo-size = <256 256 512 512 512 768 768>;
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
[all …]
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
26 host-only mode.
33 - amlogic,meson-gxl-usb-ctrl
34 - amlogic,meson-gxm-usb-ctrl
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 max-speed:
24 nvmem-cells:
29 nvmem-cell-names:
30 const: mac-address
32 phy-connection-type:
[all …]
H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
307 struct al_eth_mac_10g_stats_v3_rx rx; member
398 /* [0x20] 1/2.5/10G MAC external configuration */
400 /* [0x24] 1/2.5/10G MAC status */
420 /* [0x4c] XGMII 32 to 64 data FIFO control */
424 /* [0x54] XGMII 64 to 32 data FIFO control */
428 /* [0x5c] SerDes TX FIFO control */
430 /* [0x60] SerDes TX FIFO status */
487 * [0xc] 40G PCS,
[all …]
H A Dal_hal_eth_ec_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
64 /* [0x8] Enable FIFO operation on the EC side. */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
86 /* [0x0] Rx FIFO input controller configuration 1 */
88 /* [0x4] Rx FIFO input controller configuration 2 */
90 /* [0x8] Threshold to start reading packet from the Rx FIFO */
92 /* [0xc] Threshold to stop writing packet to the Rx FIFO */
96 /* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */
[all …]
H A Dal_hal_eth.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
136 AL_ETH_MAC_MODE_10G_SGMII, /**< SGMII using the 10G MAC, don't use*/
137 AL_ETH_MAC_MODE_XLG_LL_40G, /**< applies to 40G mode using the 40G low latency (LL) MAC */
138 AL_ETH_MAC_MODE_KR_LL_25G, /**< applies to 25G mode using the 10/25G low latency (LL) MAC */
139 AL_ETH_MAC_MODE_XLG_LL_50G, /**< applies to 50G mode using the 40/50G low latency (LL) MAC */
140 AL_ETH_MAC_MODE_XLG_LL_25G /**< applies to 25G mode using the 40/50G low latency (LL) MAC */
[all …]
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
[all …]
H A Dfsl_fman_memac.h2 * Copyright 2008-2012 Freescale Semiconductor Inc.
45 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
51 #define CMD_CFG_CNT_FRM_EN 0x00002000 /* 18 Control frame rx enable */
65 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
89 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
90 #define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */
91 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
94 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
95 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
96 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dti,tcan4x5x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Kleine-Budde <mkl@pengutronix.de>
15 - items:
16 - enum:
17 - ti,tcan4552
18 - ti,tcan4553
19 - const: ti,tcan4x5x
20 - const: ti,tcan4x5x
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ingenic/
H A Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
[all …]
H A Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
[all …]
H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
[all …]
/freebsd/sys/dev/jme/
H A Dif_jmevar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 * Tx/Rx descriptor queue base should be 16bytes aligned and
45 * should not cross 4G bytes boundary on the 64bits address
63 #define JME_TX_DESC_HIWAT (JME_TX_RING_CNT - (((JME_TX_RING_CNT) * 3) / 10))
71 (JME_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - \
72 ETHER_HDR_LEN - ETHER_CRC_LEN)
74 (ETHER_MAX_LEN + sizeof(struct ether_vlan_header) - \
75 ETHER_HDR_LEN - ETHER_CRC_LEN)
78 * is larger than its FIFO size(2K). It's also good idea to not
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_spi.c1 /*-
67 #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */
68 #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */
77 #define CTAR_FMSZ_S 27 /* Frame Size */
94 #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */
95 #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */
98 #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */
105 #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */
106 #define SPI_POPR 0x38 /* POP RX FIFO Register */
107 #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-trans.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
15 #include "iwl-debug.h"
16 #include "iwl-config.h"
18 #include "iwl-op-mode.h"
22 #include "fw/api/dbg-tlv.h"
23 #include "iwl-dbg-tlv.h"
26 #include "iwl-modparams.h"
[all …]
/freebsd/share/man/man4/
H A Duart.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
59 set RX FIFO trigger level to ``low'' (NS8250 only)
61 set RX FIFO trigger level to ``medium low'' (NS8250 only)
63 set RX FIFO trigger level to ``medium high'' (default, NS8250 only)
65 set RX FIFO trigger level to ``high'' (NS8250 only)
72 EIA RS-232C (CCITT V.24) serial communications interface.
112 It contains the bus attachments and the low-level interrupt handler.
144 .Bl -bullet -compact
[all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dreg_addr_bb.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
80 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received
81 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
[all …]
H A Dreg_addr_e5.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
80 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received
81 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
[all …]
H A Dreg_addr_k2.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
80 … 0x00381cUL //Access:R DataWidth:0x20 // Number of RX tlp are received
81 … 0x003820UL //Access:R DataWidth:0x20 // Byte number of RX are received
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
[all …]

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