xref: /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h (revision 3eb66e91a25497065c5322b1268cbc3953642227)
105491d2cSKalle Valo /*
205491d2cSKalle Valo  * Copyright (c) 2010 Broadcom Corporation
305491d2cSKalle Valo  *
405491d2cSKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
505491d2cSKalle Valo  * purpose with or without fee is hereby granted, provided that the above
605491d2cSKalle Valo  * copyright notice and this permission notice appear in all copies.
705491d2cSKalle Valo  *
805491d2cSKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
905491d2cSKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1005491d2cSKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
1105491d2cSKalle Valo  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1205491d2cSKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
1305491d2cSKalle Valo  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
1405491d2cSKalle Valo  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1505491d2cSKalle Valo  */
1605491d2cSKalle Valo 
1705491d2cSKalle Valo #ifndef _BRCM_MAIN_H_
1805491d2cSKalle Valo #define _BRCM_MAIN_H_
1905491d2cSKalle Valo 
2005491d2cSKalle Valo #include <linux/etherdevice.h>
2105491d2cSKalle Valo 
2205491d2cSKalle Valo #include <brcmu_utils.h>
2305491d2cSKalle Valo #include "types.h"
2405491d2cSKalle Valo #include "d11.h"
2505491d2cSKalle Valo #include "scb.h"
2605491d2cSKalle Valo 
2705491d2cSKalle Valo #define	INVCHANNEL		255	/* invalid channel */
2805491d2cSKalle Valo 
2905491d2cSKalle Valo /* max # brcms_c_module_register() calls */
3005491d2cSKalle Valo #define BRCMS_MAXMODULES	22
3105491d2cSKalle Valo 
3205491d2cSKalle Valo #define SEQNUM_SHIFT		4
3305491d2cSKalle Valo #define SEQNUM_MAX		0x1000
3405491d2cSKalle Valo 
3505491d2cSKalle Valo #define NTXRATE			64	/* # tx MPDUs rate is reported for */
3605491d2cSKalle Valo 
3705491d2cSKalle Valo /* Maximum wait time for a MAC suspend */
3805491d2cSKalle Valo /* uS: 83mS is max packet time (64KB ampdu @ 6Mbps) */
3905491d2cSKalle Valo #define	BRCMS_MAX_MAC_SUSPEND	83000
4005491d2cSKalle Valo 
4105491d2cSKalle Valo /* responses for probe requests older that this are tossed, zero to disable */
4205491d2cSKalle Valo #define BRCMS_PRB_RESP_TIMEOUT	0	/* Disable probe response timeout */
4305491d2cSKalle Valo 
4405491d2cSKalle Valo /* transmit buffer max headroom for protocol headers */
4505491d2cSKalle Valo #define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN)
4605491d2cSKalle Valo 
4705491d2cSKalle Valo /* Macros for doing definition and get/set of bitfields
4805491d2cSKalle Valo  * Usage example, e.g. a three-bit field (bits 4-6):
4905491d2cSKalle Valo  *    #define <NAME>_M	BITFIELD_MASK(3)
5005491d2cSKalle Valo  *    #define <NAME>_S	4
5105491d2cSKalle Valo  * ...
5205491d2cSKalle Valo  *    regval = R_REG(osh, &regs->regfoo);
5305491d2cSKalle Valo  *    field = GFIELD(regval, <NAME>);
5405491d2cSKalle Valo  *    regval = SFIELD(regval, <NAME>, 1);
5505491d2cSKalle Valo  *    W_REG(osh, &regs->regfoo, regval);
5605491d2cSKalle Valo  */
5705491d2cSKalle Valo #define BITFIELD_MASK(width) \
5805491d2cSKalle Valo 		(((unsigned)1 << (width)) - 1)
5905491d2cSKalle Valo #define GFIELD(val, field) \
6005491d2cSKalle Valo 		(((val) >> field ## _S) & field ## _M)
6105491d2cSKalle Valo #define SFIELD(val, field, bits) \
6205491d2cSKalle Valo 		(((val) & (~(field ## _M << field ## _S))) | \
6305491d2cSKalle Valo 		 ((unsigned)(bits) << field ## _S))
6405491d2cSKalle Valo 
6505491d2cSKalle Valo #define	SW_TIMER_MAC_STAT_UPD		30	/* periodic MAC stats update */
6605491d2cSKalle Valo 
6705491d2cSKalle Valo /* max # supported core revisions (0 .. MAXCOREREV - 1) */
6805491d2cSKalle Valo #define	MAXCOREREV		28
6905491d2cSKalle Valo 
7005491d2cSKalle Valo /* Double check that unsupported cores are not enabled */
7105491d2cSKalle Valo #if CONF_MSK(D11CONF, 0x4f) || CONF_GE(D11CONF, MAXCOREREV)
7205491d2cSKalle Valo #error "Configuration for D11CONF includes unsupported versions."
7305491d2cSKalle Valo #endif				/* Bad versions */
7405491d2cSKalle Valo 
7505491d2cSKalle Valo /* values for shortslot_override */
7605491d2cSKalle Valo #define BRCMS_SHORTSLOT_AUTO	-1 /* Driver will manage Shortslot setting */
7705491d2cSKalle Valo #define BRCMS_SHORTSLOT_OFF	0  /* Turn off short slot */
7805491d2cSKalle Valo #define BRCMS_SHORTSLOT_ON	1  /* Turn on short slot */
7905491d2cSKalle Valo 
8005491d2cSKalle Valo /* value for short/long and mixmode/greenfield preamble */
8105491d2cSKalle Valo #define BRCMS_LONG_PREAMBLE	(0)
8205491d2cSKalle Valo #define BRCMS_SHORT_PREAMBLE	(1 << 0)
8305491d2cSKalle Valo #define BRCMS_GF_PREAMBLE		(1 << 1)
8405491d2cSKalle Valo #define BRCMS_MM_PREAMBLE		(1 << 2)
8505491d2cSKalle Valo #define BRCMS_IS_MIMO_PREAMBLE(_pre) (((_pre) == BRCMS_GF_PREAMBLE) || \
8605491d2cSKalle Valo 				      ((_pre) == BRCMS_MM_PREAMBLE))
8705491d2cSKalle Valo 
8805491d2cSKalle Valo /* TxFrameID */
8905491d2cSKalle Valo /* seq and frag bits: SEQNUM_SHIFT, FRAGNUM_MASK (802.11.h) */
9005491d2cSKalle Valo /* rate epoch bits: TXFID_RATE_SHIFT, TXFID_RATE_MASK ((wlc_rate.c) */
9105491d2cSKalle Valo #define TXFID_QUEUE_MASK	0x0007	/* Bits 0-2 */
9205491d2cSKalle Valo #define TXFID_SEQ_MASK		0x7FE0	/* Bits 5-15 */
9305491d2cSKalle Valo #define TXFID_SEQ_SHIFT		5	/* Number of bit shifts */
9405491d2cSKalle Valo #define	TXFID_RATE_PROBE_MASK	0x8000	/* Bit 15 for rate probe */
9505491d2cSKalle Valo #define TXFID_RATE_MASK		0x0018	/* Mask for bits 3 and 4 */
9605491d2cSKalle Valo #define TXFID_RATE_SHIFT	3	/* Shift 3 bits for rate mask */
9705491d2cSKalle Valo 
9805491d2cSKalle Valo /* promote boardrev */
9905491d2cSKalle Valo #define BOARDREV_PROMOTABLE	0xFF	/* from */
10005491d2cSKalle Valo #define BOARDREV_PROMOTED	1	/* to */
10105491d2cSKalle Valo 
10205491d2cSKalle Valo #define DATA_BLOCK_TX_SUPR	(1 << 4)
10305491d2cSKalle Valo 
10405491d2cSKalle Valo /* Ucode MCTL_WAKE override bits */
10505491d2cSKalle Valo #define BRCMS_WAKE_OVERRIDE_CLKCTL	0x01
10605491d2cSKalle Valo #define BRCMS_WAKE_OVERRIDE_PHYREG	0x02
10705491d2cSKalle Valo #define BRCMS_WAKE_OVERRIDE_MACSUSPEND	0x04
10805491d2cSKalle Valo #define BRCMS_WAKE_OVERRIDE_TXFIFO	0x08
10905491d2cSKalle Valo #define BRCMS_WAKE_OVERRIDE_FORCEFAST	0x10
11005491d2cSKalle Valo 
11105491d2cSKalle Valo /* stuff pulled in from wlc.c */
11205491d2cSKalle Valo 
11305491d2cSKalle Valo /* Interrupt bit error summary.  Don't include I_RU: we refill DMA at other
11405491d2cSKalle Valo  * times; and if we run out, constant I_RU interrupts may cause lockup.  We
11505491d2cSKalle Valo  * will still get error counts from rx0ovfl.
11605491d2cSKalle Valo  */
11705491d2cSKalle Valo #define	I_ERRORS	(I_PC | I_PD | I_DE | I_RO | I_XU)
11805491d2cSKalle Valo /* default software intmasks */
11905491d2cSKalle Valo #define	DEF_RXINTMASK	(I_RI)	/* enable rx int on rxfifo only */
12005491d2cSKalle Valo #define	DEF_MACINTMASK	(MI_TXSTOP | MI_TBTT | MI_ATIMWINEND | MI_PMQ | \
12105491d2cSKalle Valo 			 MI_PHYTXERR | MI_DMAINT | MI_TFS | MI_BG_NOISE | \
12205491d2cSKalle Valo 			 MI_CCA | MI_TO | MI_GP0 | MI_RFDISABLE | MI_PWRUP)
12305491d2cSKalle Valo 
12405491d2cSKalle Valo #define	MAXTXPKTS		6	/* max # pkts pending */
12505491d2cSKalle Valo 
12605491d2cSKalle Valo /* frameburst */
12705491d2cSKalle Valo #define	MAXTXFRAMEBURST		8 /* vanilla xpress mode: max frames/burst */
12805491d2cSKalle Valo #define	MAXFRAMEBURST_TXOP	10000	/* Frameburst TXOP in usec */
12905491d2cSKalle Valo 
13005491d2cSKalle Valo #define	NFIFO			6	/* # tx/rx fifopairs */
13105491d2cSKalle Valo 
13205491d2cSKalle Valo /* PLL requests */
13305491d2cSKalle Valo 
13405491d2cSKalle Valo /* pll is shared on old chips */
13505491d2cSKalle Valo #define BRCMS_PLLREQ_SHARED	0x1
13605491d2cSKalle Valo /* hold pll for radio monitor register checking */
13705491d2cSKalle Valo #define BRCMS_PLLREQ_RADIO_MON	0x2
13805491d2cSKalle Valo /* hold/release pll for some short operation */
13905491d2cSKalle Valo #define BRCMS_PLLREQ_FLIP		0x4
14005491d2cSKalle Valo 
14105491d2cSKalle Valo #define	CHANNEL_BANDUNIT(wlc, ch) \
14205491d2cSKalle Valo 	(((ch) <= CH_MAX_2G_CHANNEL) ? BAND_2G_INDEX : BAND_5G_INDEX)
14305491d2cSKalle Valo 
14405491d2cSKalle Valo #define	OTHERBANDUNIT(wlc) \
14505491d2cSKalle Valo 	((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
14605491d2cSKalle Valo 
14705491d2cSKalle Valo /*
14805491d2cSKalle Valo  * 802.11 protection information
14905491d2cSKalle Valo  *
15005491d2cSKalle Valo  * _g: use g spec protection, driver internal.
15105491d2cSKalle Valo  * g_override: override for use of g spec protection.
15205491d2cSKalle Valo  * gmode_user: user config gmode, operating band->gmode is different.
15305491d2cSKalle Valo  * overlap: Overlap BSS/IBSS protection for both 11g and 11n.
15405491d2cSKalle Valo  * nmode_user: user config nmode, operating pub->nmode is different.
15505491d2cSKalle Valo  * n_cfg: use OFDM protection on MIMO frames.
15605491d2cSKalle Valo  * n_cfg_override: override for use of N protection.
15705491d2cSKalle Valo  * nongf: non-GF present protection.
15805491d2cSKalle Valo  * nongf_override: override for use of GF protection.
15905491d2cSKalle Valo  * n_pam_override: override for preamble: MM or GF.
16005491d2cSKalle Valo  * n_obss: indicated OBSS Non-HT STA present.
16105491d2cSKalle Valo */
16205491d2cSKalle Valo struct brcms_protection {
16305491d2cSKalle Valo 	bool _g;
16405491d2cSKalle Valo 	s8 g_override;
16505491d2cSKalle Valo 	u8 gmode_user;
16605491d2cSKalle Valo 	s8 overlap;
16705491d2cSKalle Valo 	s8 nmode_user;
16805491d2cSKalle Valo 	s8 n_cfg;
16905491d2cSKalle Valo 	s8 n_cfg_override;
17005491d2cSKalle Valo 	bool nongf;
17105491d2cSKalle Valo 	s8 nongf_override;
17205491d2cSKalle Valo 	s8 n_pam_override;
17305491d2cSKalle Valo 	bool n_obss;
17405491d2cSKalle Valo };
17505491d2cSKalle Valo 
17605491d2cSKalle Valo /*
17705491d2cSKalle Valo  * anything affecting the single/dual streams/antenna operation
17805491d2cSKalle Valo  *
17905491d2cSKalle Valo  * hw_txchain: HW txchain bitmap cfg.
18005491d2cSKalle Valo  * txchain: txchain bitmap being used.
18105491d2cSKalle Valo  * txstreams: number of txchains being used.
18205491d2cSKalle Valo  * hw_rxchain: HW rxchain bitmap cfg.
18305491d2cSKalle Valo  * rxchain: rxchain bitmap being used.
18405491d2cSKalle Valo  * rxstreams: number of rxchains being used.
18505491d2cSKalle Valo  * ant_rx_ovr: rx antenna override.
18605491d2cSKalle Valo  * txant: userTx antenna setting.
18705491d2cSKalle Valo  * phytxant: phyTx antenna setting in txheader.
18805491d2cSKalle Valo  * ss_opmode: singlestream Operational mode, 0:siso; 1:cdd.
18905491d2cSKalle Valo  * ss_algosel_auto: if true, use wlc->stf->ss_algo_channel;
19005491d2cSKalle Valo  *			else use wlc->band->stf->ss_mode_band.
19105491d2cSKalle Valo  * ss_algo_channel: ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC.
19205491d2cSKalle Valo  * rxchain_restore_delay: delay time to restore default rxchain.
19305491d2cSKalle Valo  * ldpc: AUTO/ON/OFF ldpc cap supported.
19405491d2cSKalle Valo  * txcore[MAX_STREAMS_SUPPORTED + 1]: bitmap of selected core for each Nsts.
19505491d2cSKalle Valo  * spatial_policy:
19605491d2cSKalle Valo  */
19705491d2cSKalle Valo struct brcms_stf {
19805491d2cSKalle Valo 	u8 hw_txchain;
19905491d2cSKalle Valo 	u8 txchain;
20005491d2cSKalle Valo 	u8 txstreams;
20105491d2cSKalle Valo 	u8 hw_rxchain;
20205491d2cSKalle Valo 	u8 rxchain;
20305491d2cSKalle Valo 	u8 rxstreams;
20405491d2cSKalle Valo 	u8 ant_rx_ovr;
20505491d2cSKalle Valo 	s8 txant;
20605491d2cSKalle Valo 	u16 phytxant;
20705491d2cSKalle Valo 	u8 ss_opmode;
20805491d2cSKalle Valo 	bool ss_algosel_auto;
20905491d2cSKalle Valo 	u16 ss_algo_channel;
21005491d2cSKalle Valo 	u8 rxchain_restore_delay;
21105491d2cSKalle Valo 	s8 ldpc;
21205491d2cSKalle Valo 	u8 txcore[MAX_STREAMS_SUPPORTED + 1];
21305491d2cSKalle Valo 	s8 spatial_policy;
21405491d2cSKalle Valo };
21505491d2cSKalle Valo 
21605491d2cSKalle Valo #define BRCMS_STF_SS_STBC_TX(wlc, scb) \
21705491d2cSKalle Valo 	(((wlc)->stf->txstreams > 1) && (((wlc)->band->band_stf_stbc_tx == ON) \
21805491d2cSKalle Valo 	 || (((scb)->flags & SCB_STBCCAP) && \
21905491d2cSKalle Valo 	     (wlc)->band->band_stf_stbc_tx == AUTO && \
22005491d2cSKalle Valo 	     isset(&((wlc)->stf->ss_algo_channel), PHY_TXC1_MODE_STBC))))
22105491d2cSKalle Valo 
22205491d2cSKalle Valo #define BRCMS_STBC_CAP_PHY(wlc) (BRCMS_ISNPHY(wlc->band) && \
22305491d2cSKalle Valo 				 NREV_GE(wlc->band->phyrev, 3))
22405491d2cSKalle Valo 
22505491d2cSKalle Valo #define BRCMS_SGI_CAP_PHY(wlc) ((BRCMS_ISNPHY(wlc->band) && \
22605491d2cSKalle Valo 				 NREV_GE(wlc->band->phyrev, 3)) || \
22705491d2cSKalle Valo 				BRCMS_ISLCNPHY(wlc->band))
22805491d2cSKalle Valo 
22905491d2cSKalle Valo #define BRCMS_CHAN_PHYTYPE(x)     (((x) & RXS_CHAN_PHYTYPE_MASK) \
23005491d2cSKalle Valo 				   >> RXS_CHAN_PHYTYPE_SHIFT)
23105491d2cSKalle Valo #define BRCMS_CHAN_CHANNEL(x)     (((x) & RXS_CHAN_ID_MASK) \
23205491d2cSKalle Valo 				   >> RXS_CHAN_ID_SHIFT)
23305491d2cSKalle Valo 
23405491d2cSKalle Valo /*
23505491d2cSKalle Valo  * core state (mac)
23605491d2cSKalle Valo  */
23705491d2cSKalle Valo struct brcms_core {
23805491d2cSKalle Valo 	uint coreidx;		/* # sb enumerated core */
23905491d2cSKalle Valo 
24005491d2cSKalle Valo 	/* fifo */
24105491d2cSKalle Valo 	uint *txavail[NFIFO];	/* # tx descriptors available */
24205491d2cSKalle Valo 
24305491d2cSKalle Valo 	struct macstat *macstat_snapshot;	/* mac hw prev read values */
24405491d2cSKalle Valo };
24505491d2cSKalle Valo 
24605491d2cSKalle Valo /*
24705491d2cSKalle Valo  * band state (phy+ana+radio)
24805491d2cSKalle Valo  */
24905491d2cSKalle Valo struct brcms_band {
25005491d2cSKalle Valo 	int bandtype;		/* BRCM_BAND_2G, BRCM_BAND_5G */
25105491d2cSKalle Valo 	uint bandunit;		/* bandstate[] index */
25205491d2cSKalle Valo 
25305491d2cSKalle Valo 	u16 phytype;		/* phytype */
25405491d2cSKalle Valo 	u16 phyrev;
25505491d2cSKalle Valo 	u16 radioid;
25605491d2cSKalle Valo 	u16 radiorev;
25705491d2cSKalle Valo 	struct brcms_phy_pub *pi; /* pointer to phy specific information */
25805491d2cSKalle Valo 	bool abgphy_encore;
25905491d2cSKalle Valo 
26005491d2cSKalle Valo 	u8 gmode;		/* currently active gmode */
26105491d2cSKalle Valo 
26205491d2cSKalle Valo 	struct scb *hwrs_scb;	/* permanent scb for hw rateset */
26305491d2cSKalle Valo 
26405491d2cSKalle Valo 	/* band-specific copy of default_bss.rateset */
26505491d2cSKalle Valo 	struct brcms_c_rateset defrateset;
26605491d2cSKalle Valo 
26705491d2cSKalle Valo 	u8 band_stf_ss_mode;	/* Configured STF type, 0:siso; 1:cdd */
26805491d2cSKalle Valo 	s8 band_stf_stbc_tx;	/* STBC TX 0:off; 1:force on; -1:auto */
26905491d2cSKalle Valo 	/* rates supported by chip (phy-specific) */
27005491d2cSKalle Valo 	struct brcms_c_rateset hw_rateset;
27105491d2cSKalle Valo 	u8 basic_rate[BRCM_MAXRATE + 1]; /* basic rates indexed by rate */
27205491d2cSKalle Valo 	bool mimo_cap_40;	/* 40 MHz cap enabled on this band */
27305491d2cSKalle Valo 	s8 antgain;		/* antenna gain from srom */
27405491d2cSKalle Valo 
27505491d2cSKalle Valo 	u16 CWmin; /* minimum size of contention window, in unit of aSlotTime */
27605491d2cSKalle Valo 	u16 CWmax; /* maximum size of contention window, in unit of aSlotTime */
27705491d2cSKalle Valo 	struct ieee80211_supported_band band;
27805491d2cSKalle Valo };
27905491d2cSKalle Valo 
28005491d2cSKalle Valo /* module control blocks */
28105491d2cSKalle Valo struct modulecb {
28205491d2cSKalle Valo 	/* module name : NULL indicates empty array member */
28305491d2cSKalle Valo 	char name[32];
28405491d2cSKalle Valo 	/* handle passed when handler 'doiovar' is called */
28505491d2cSKalle Valo 	struct brcms_info *hdl;
28605491d2cSKalle Valo 
28705491d2cSKalle Valo 	int (*down_fn)(void *handle); /* down handler. Note: the int returned
28805491d2cSKalle Valo 				       * by the down function is a count of the
28905491d2cSKalle Valo 				       * number of timers that could not be
29005491d2cSKalle Valo 				       * freed.
29105491d2cSKalle Valo 				       */
29205491d2cSKalle Valo 
29305491d2cSKalle Valo };
29405491d2cSKalle Valo 
29505491d2cSKalle Valo struct brcms_hw_band {
29605491d2cSKalle Valo 	int bandtype;		/* BRCM_BAND_2G, BRCM_BAND_5G */
29705491d2cSKalle Valo 	uint bandunit;		/* bandstate[] index */
29805491d2cSKalle Valo 	u16 mhfs[MHFMAX];	/* MHF array shadow */
29905491d2cSKalle Valo 	u8 bandhw_stf_ss_mode;	/* HW configured STF type, 0:siso; 1:cdd */
30005491d2cSKalle Valo 	u16 CWmin;
30105491d2cSKalle Valo 	u16 CWmax;
30205491d2cSKalle Valo 	u32 core_flags;
30305491d2cSKalle Valo 
30405491d2cSKalle Valo 	u16 phytype;		/* phytype */
30505491d2cSKalle Valo 	u16 phyrev;
30605491d2cSKalle Valo 	u16 radioid;
30705491d2cSKalle Valo 	u16 radiorev;
30805491d2cSKalle Valo 	struct brcms_phy_pub *pi; /* pointer to phy specific information */
30905491d2cSKalle Valo 	bool abgphy_encore;
31005491d2cSKalle Valo };
31105491d2cSKalle Valo 
31205491d2cSKalle Valo struct brcms_hardware {
31305491d2cSKalle Valo 	bool _piomode;		/* true if pio mode */
31405491d2cSKalle Valo 	struct brcms_c_info *wlc;
31505491d2cSKalle Valo 
31605491d2cSKalle Valo 	/* fifo */
31705491d2cSKalle Valo 	struct dma_pub *di[NFIFO];	/* dma handles, per fifo */
31805491d2cSKalle Valo 
31905491d2cSKalle Valo 	uint unit;		/* device instance number */
32005491d2cSKalle Valo 
32105491d2cSKalle Valo 	/* version info */
32205491d2cSKalle Valo 	u16 vendorid;	/* PCI vendor id */
32305491d2cSKalle Valo 	u16 deviceid;	/* PCI device id */
32405491d2cSKalle Valo 	uint corerev;		/* core revision */
32505491d2cSKalle Valo 	u8 sromrev;		/* version # of the srom */
32605491d2cSKalle Valo 	u16 boardrev;	/* version # of particular board */
32705491d2cSKalle Valo 	u32 boardflags;	/* Board specific flags from srom */
32805491d2cSKalle Valo 	u32 boardflags2;	/* More board flags if sromrev >= 4 */
32905491d2cSKalle Valo 	u32 machwcap;	/* MAC capabilities */
33005491d2cSKalle Valo 	u32 machwcap_backup;	/* backup of machwcap */
33105491d2cSKalle Valo 
33205491d2cSKalle Valo 	struct si_pub *sih;	/* SI handle (cookie for siutils calls) */
33305491d2cSKalle Valo 	struct bcma_device *d11core;	/* pointer to 802.11 core */
33405491d2cSKalle Valo 	struct phy_shim_info *physhim; /* phy shim layer handler */
33505491d2cSKalle Valo 	struct shared_phy *phy_sh;	/* pointer to shared phy state */
33605491d2cSKalle Valo 	struct brcms_hw_band *band;/* pointer to active per-band state */
33705491d2cSKalle Valo 	/* band state per phy/radio */
33805491d2cSKalle Valo 	struct brcms_hw_band *bandstate[MAXBANDS];
33905491d2cSKalle Valo 	u16 bmac_phytxant;	/* cache of high phytxant state */
34005491d2cSKalle Valo 	bool shortslot;		/* currently using 11g ShortSlot timing */
34105491d2cSKalle Valo 	u16 SRL;		/* 802.11 dot11ShortRetryLimit */
34205491d2cSKalle Valo 	u16 LRL;		/* 802.11 dot11LongRetryLimit */
34305491d2cSKalle Valo 	u16 SFBL;		/* Short Frame Rate Fallback Limit */
34405491d2cSKalle Valo 	u16 LFBL;		/* Long Frame Rate Fallback Limit */
34505491d2cSKalle Valo 
34605491d2cSKalle Valo 	bool up;		/* d11 hardware up and running */
34705491d2cSKalle Valo 	uint now;		/* # elapsed seconds */
34805491d2cSKalle Valo 	uint _nbands;		/* # bands supported */
34905491d2cSKalle Valo 	u16 chanspec;	/* bmac chanspec shadow */
35005491d2cSKalle Valo 
35105491d2cSKalle Valo 	uint *txavail[NFIFO];	/* # tx descriptors available */
35205491d2cSKalle Valo 	const u16 *xmtfifo_sz;	/* fifo size in 256B for each xmt fifo */
35305491d2cSKalle Valo 
35405491d2cSKalle Valo 	u32 pllreq;		/* pll requests to keep PLL on */
35505491d2cSKalle Valo 
35605491d2cSKalle Valo 	u8 suspended_fifos;	/* Which TX fifo to remain awake for */
35705491d2cSKalle Valo 	u32 maccontrol;	/* Cached value of maccontrol */
35805491d2cSKalle Valo 	uint mac_suspend_depth;	/* current depth of mac_suspend levels */
35905491d2cSKalle Valo 	u32 wake_override;	/* bit flags to force MAC to WAKE mode */
36005491d2cSKalle Valo 	u32 mute_override;	/* Prevent ucode from sending beacons */
36105491d2cSKalle Valo 	u8 etheraddr[ETH_ALEN];	/* currently configured ethernet address */
36205491d2cSKalle Valo 	bool noreset;		/* true= do not reset hw, used by WLC_OUT */
36305491d2cSKalle Valo 	bool forcefastclk;	/* true if h/w is forcing to use fast clk */
36405491d2cSKalle Valo 	bool clk;		/* core is out of reset and has clock */
36505491d2cSKalle Valo 	bool sbclk;		/* sb has clock */
36605491d2cSKalle Valo 	bool phyclk;		/* phy is out of reset and has clock */
36705491d2cSKalle Valo 
36805491d2cSKalle Valo 	bool ucode_loaded;	/* true after ucode downloaded */
36905491d2cSKalle Valo 
37005491d2cSKalle Valo 
37105491d2cSKalle Valo 	u8 hw_stf_ss_opmode;	/* STF single stream operation mode */
37205491d2cSKalle Valo 	u8 antsel_type;	/* Type of boardlevel mimo antenna switch-logic
37305491d2cSKalle Valo 				 * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
37405491d2cSKalle Valo 				 */
37505491d2cSKalle Valo 	u32 antsel_avail;	/*
37605491d2cSKalle Valo 				 * put struct antsel_info here if more info is
37705491d2cSKalle Valo 				 * needed
37805491d2cSKalle Valo 				 */
37905491d2cSKalle Valo };
38005491d2cSKalle Valo 
38105491d2cSKalle Valo /*
38205491d2cSKalle Valo  * Principal common driver data structure.
38305491d2cSKalle Valo  *
38405491d2cSKalle Valo  * pub: pointer to driver public state.
38505491d2cSKalle Valo  * wl: pointer to specific private state.
38605491d2cSKalle Valo  * hw: HW related state.
38705491d2cSKalle Valo  * clkreq_override: setting for clkreq for PCIE : Auto, 0, 1.
38805491d2cSKalle Valo  * fastpwrup_dly: time in us needed to bring up d11 fast clock.
38905491d2cSKalle Valo  * macintstatus: bit channel between isr and dpc.
39005491d2cSKalle Valo  * macintmask: sw runtime master macintmask value.
39105491d2cSKalle Valo  * defmacintmask: default "on" macintmask value.
39205491d2cSKalle Valo  * clk: core is out of reset and has clock.
39305491d2cSKalle Valo  * core: pointer to active io core.
39405491d2cSKalle Valo  * band: pointer to active per-band state.
39505491d2cSKalle Valo  * corestate: per-core state (one per hw core).
39605491d2cSKalle Valo  * bandstate: per-band state (one per phy/radio).
39705491d2cSKalle Valo  * qvalid: DirFrmQValid and BcMcFrmQValid.
39805491d2cSKalle Valo  * ampdu: ampdu module handler.
39905491d2cSKalle Valo  * asi: antsel module handler.
40005491d2cSKalle Valo  * cmi: channel manager module handler.
40105491d2cSKalle Valo  * vendorid: PCI vendor id.
40205491d2cSKalle Valo  * deviceid: PCI device id.
40305491d2cSKalle Valo  * ucode_rev: microcode revision.
40405491d2cSKalle Valo  * machwcap: MAC capabilities, BMAC shadow.
40505491d2cSKalle Valo  * perm_etheraddr: original sprom local ethernet address.
40605491d2cSKalle Valo  * bandlocked: disable auto multi-band switching.
40705491d2cSKalle Valo  * bandinit_pending: track band init in auto band.
40805491d2cSKalle Valo  * radio_monitor: radio timer is running.
40905491d2cSKalle Valo  * going_down: down path intermediate variable.
41005491d2cSKalle Valo  * wdtimer: timer for watchdog routine.
41105491d2cSKalle Valo  * radio_timer: timer for hw radio button monitor routine.
41205491d2cSKalle Valo  * monitor: monitor (MPDU sniffing) mode.
41305491d2cSKalle Valo  * bcnmisc_monitor: bcns promisc mode override for monitor.
41405491d2cSKalle Valo  * _rifs: enable per-packet rifs.
41505491d2cSKalle Valo  * bcn_li_bcn: beacon listen interval in # beacons.
41605491d2cSKalle Valo  * bcn_li_dtim: beacon listen interval in # dtims.
41705491d2cSKalle Valo  * WDarmed: watchdog timer is armed.
41805491d2cSKalle Valo  * WDlast: last time wlc_watchdog() was called.
41905491d2cSKalle Valo  * edcf_txop[IEEE80211_NUM_ACS]: current txop for each ac.
42005491d2cSKalle Valo  * wme_retries: per-AC retry limits.
42105491d2cSKalle Valo  * bsscfg: set of BSS configurations, idx 0 is default and always valid.
42205491d2cSKalle Valo  * cfg: the primary bsscfg (can be AP or STA).
42305491d2cSKalle Valo  * modulecb:
42405491d2cSKalle Valo  * mimoft: SIGN or 11N.
42505491d2cSKalle Valo  * cck_40txbw: 11N, cck tx b/w override when in 40MHZ mode.
42605491d2cSKalle Valo  * ofdm_40txbw: 11N, ofdm tx b/w override when in 40MHZ mode.
42705491d2cSKalle Valo  * mimo_40txbw: 11N, mimo tx b/w override when in 40MHZ mode.
42805491d2cSKalle Valo  * default_bss: configured BSS parameters.
42905491d2cSKalle Valo  * mc_fid_counter: BC/MC FIFO frame ID counter.
43005491d2cSKalle Valo  * country_default: saved country for leaving 802.11d auto-country mode.
43105491d2cSKalle Valo  * autocountry_default: initial country for 802.11d auto-country mode.
43205491d2cSKalle Valo  * prb_resp_timeout: do not send prb resp if request older
43305491d2cSKalle Valo  *		     than this, 0 = disable.
43405491d2cSKalle Valo  * home_chanspec: shared home chanspec.
43505491d2cSKalle Valo  * chanspec: target operational channel.
43605491d2cSKalle Valo  * usr_fragthresh: user configured fragmentation threshold.
43705491d2cSKalle Valo  * fragthresh[NFIFO]: per-fifo fragmentation thresholds.
43805491d2cSKalle Valo  * RTSThresh: 802.11 dot11RTSThreshold.
43905491d2cSKalle Valo  * SRL: 802.11 dot11ShortRetryLimit.
44005491d2cSKalle Valo  * LRL: 802.11 dot11LongRetryLimit.
44105491d2cSKalle Valo  * SFBL: Short Frame Rate Fallback Limit.
44205491d2cSKalle Valo  * LFBL: Long Frame Rate Fallback Limit.
44305491d2cSKalle Valo  * shortslot: currently using 11g ShortSlot timing.
44405491d2cSKalle Valo  * shortslot_override: 11g ShortSlot override.
44505491d2cSKalle Valo  * include_legacy_erp: include Legacy ERP info elt ID 47 as well as g ID 42.
44605491d2cSKalle Valo  * PLCPHdr_override: 802.11b Preamble Type override.
44705491d2cSKalle Valo  * stf:
44805491d2cSKalle Valo  * bcn_rspec: save bcn ratespec purpose.
44905491d2cSKalle Valo  * tempsense_lasttime;
45005491d2cSKalle Valo  * tx_duty_cycle_ofdm: maximum allowed duty cycle for OFDM.
45105491d2cSKalle Valo  * tx_duty_cycle_cck: maximum allowed duty cycle for CCK.
45205491d2cSKalle Valo  * wiphy:
45305491d2cSKalle Valo  * pri_scb: primary Station Control Block
45405491d2cSKalle Valo  */
45505491d2cSKalle Valo struct brcms_c_info {
45605491d2cSKalle Valo 	struct brcms_pub *pub;
45705491d2cSKalle Valo 	struct brcms_info *wl;
45805491d2cSKalle Valo 	struct brcms_hardware *hw;
45905491d2cSKalle Valo 
46005491d2cSKalle Valo 	/* clock */
46105491d2cSKalle Valo 	u16 fastpwrup_dly;
46205491d2cSKalle Valo 
46305491d2cSKalle Valo 	/* interrupt */
46405491d2cSKalle Valo 	u32 macintstatus;
46505491d2cSKalle Valo 	u32 macintmask;
46605491d2cSKalle Valo 	u32 defmacintmask;
46705491d2cSKalle Valo 
46805491d2cSKalle Valo 	bool clk;
46905491d2cSKalle Valo 
47005491d2cSKalle Valo 	/* multiband */
47105491d2cSKalle Valo 	struct brcms_core *core;
47205491d2cSKalle Valo 	struct brcms_band *band;
47305491d2cSKalle Valo 	struct brcms_core *corestate;
47405491d2cSKalle Valo 	struct brcms_band *bandstate[MAXBANDS];
47505491d2cSKalle Valo 
47605491d2cSKalle Valo 	/* packet queue */
47705491d2cSKalle Valo 	uint qvalid;
47805491d2cSKalle Valo 
47905491d2cSKalle Valo 	struct ampdu_info *ampdu;
48005491d2cSKalle Valo 	struct antsel_info *asi;
48105491d2cSKalle Valo 	struct brcms_cm_info *cmi;
48205491d2cSKalle Valo 
48305491d2cSKalle Valo 	u16 vendorid;
48405491d2cSKalle Valo 	u16 deviceid;
48505491d2cSKalle Valo 	uint ucode_rev;
48605491d2cSKalle Valo 
48705491d2cSKalle Valo 	u8 perm_etheraddr[ETH_ALEN];
48805491d2cSKalle Valo 
48905491d2cSKalle Valo 	bool bandlocked;
49005491d2cSKalle Valo 	bool bandinit_pending;
49105491d2cSKalle Valo 
49205491d2cSKalle Valo 	bool radio_monitor;
49305491d2cSKalle Valo 	bool going_down;
49405491d2cSKalle Valo 
49505491d2cSKalle Valo 	bool beacon_template_virgin;
49605491d2cSKalle Valo 
49705491d2cSKalle Valo 	struct brcms_timer *wdtimer;
49805491d2cSKalle Valo 	struct brcms_timer *radio_timer;
49905491d2cSKalle Valo 
50005491d2cSKalle Valo 	/* promiscuous */
50105491d2cSKalle Valo 	uint filter_flags;
50205491d2cSKalle Valo 
50305491d2cSKalle Valo 	/* driver feature */
50405491d2cSKalle Valo 	bool _rifs;
50505491d2cSKalle Valo 
50605491d2cSKalle Valo 	/* AP-STA synchronization, power save */
50705491d2cSKalle Valo 	u8 bcn_li_bcn;
50805491d2cSKalle Valo 	u8 bcn_li_dtim;
50905491d2cSKalle Valo 
51005491d2cSKalle Valo 	bool WDarmed;
51105491d2cSKalle Valo 	u32 WDlast;
51205491d2cSKalle Valo 
51305491d2cSKalle Valo 	/* WME */
51405491d2cSKalle Valo 	u16 edcf_txop[IEEE80211_NUM_ACS];
51505491d2cSKalle Valo 
51605491d2cSKalle Valo 	u16 wme_retries[IEEE80211_NUM_ACS];
51705491d2cSKalle Valo 
51805491d2cSKalle Valo 	struct brcms_bss_cfg *bsscfg;
51905491d2cSKalle Valo 
52005491d2cSKalle Valo 	struct modulecb *modulecb;
52105491d2cSKalle Valo 
52205491d2cSKalle Valo 	u8 mimoft;
52305491d2cSKalle Valo 	s8 cck_40txbw;
52405491d2cSKalle Valo 	s8 ofdm_40txbw;
52505491d2cSKalle Valo 	s8 mimo_40txbw;
52605491d2cSKalle Valo 
52705491d2cSKalle Valo 	struct brcms_bss_info *default_bss;
52805491d2cSKalle Valo 
52905491d2cSKalle Valo 	u16 mc_fid_counter;
53005491d2cSKalle Valo 
53105491d2cSKalle Valo 	char country_default[BRCM_CNTRY_BUF_SZ];
53205491d2cSKalle Valo 	char autocountry_default[BRCM_CNTRY_BUF_SZ];
53305491d2cSKalle Valo 	u16 prb_resp_timeout;
53405491d2cSKalle Valo 
53505491d2cSKalle Valo 	u16 home_chanspec;
53605491d2cSKalle Valo 
53705491d2cSKalle Valo 	/* PHY parameters */
53805491d2cSKalle Valo 	u16 chanspec;
53905491d2cSKalle Valo 	u16 usr_fragthresh;
54005491d2cSKalle Valo 	u16 fragthresh[NFIFO];
54105491d2cSKalle Valo 	u16 RTSThresh;
54205491d2cSKalle Valo 	u16 SRL;
54305491d2cSKalle Valo 	u16 LRL;
54405491d2cSKalle Valo 	u16 SFBL;
54505491d2cSKalle Valo 	u16 LFBL;
54605491d2cSKalle Valo 
54705491d2cSKalle Valo 	/* network config */
54805491d2cSKalle Valo 	bool shortslot;
54905491d2cSKalle Valo 	s8 shortslot_override;
55005491d2cSKalle Valo 	bool include_legacy_erp;
55105491d2cSKalle Valo 
55205491d2cSKalle Valo 	struct brcms_protection *protection;
55305491d2cSKalle Valo 	s8 PLCPHdr_override;
55405491d2cSKalle Valo 
55505491d2cSKalle Valo 	struct brcms_stf *stf;
55605491d2cSKalle Valo 
55705491d2cSKalle Valo 	u32 bcn_rspec;
55805491d2cSKalle Valo 
55905491d2cSKalle Valo 	uint tempsense_lasttime;
56005491d2cSKalle Valo 
56105491d2cSKalle Valo 	u16 tx_duty_cycle_ofdm;
56205491d2cSKalle Valo 	u16 tx_duty_cycle_cck;
56305491d2cSKalle Valo 
56405491d2cSKalle Valo 	struct wiphy *wiphy;
56505491d2cSKalle Valo 	struct scb pri_scb;
566*2258ee58SAli MJ Al-Nasrawy 	struct ieee80211_vif *vif;
56705491d2cSKalle Valo 
56805491d2cSKalle Valo 	struct sk_buff *beacon;
56905491d2cSKalle Valo 	u16 beacon_tim_offset;
57005491d2cSKalle Valo 	u16 beacon_dtim_period;
57105491d2cSKalle Valo 	struct sk_buff *probe_resp;
57205491d2cSKalle Valo };
57305491d2cSKalle Valo 
57405491d2cSKalle Valo /* antsel module specific state */
57505491d2cSKalle Valo struct antsel_info {
57605491d2cSKalle Valo 	struct brcms_c_info *wlc;	/* pointer to main wlc structure */
57705491d2cSKalle Valo 	struct brcms_pub *pub;		/* pointer to public fn */
57805491d2cSKalle Valo 	u8 antsel_type;	/* Type of boardlevel mimo antenna switch-logic
57905491d2cSKalle Valo 				 * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
58005491d2cSKalle Valo 				 */
58105491d2cSKalle Valo 	u8 antsel_antswitch;	/* board level antenna switch type */
58205491d2cSKalle Valo 	bool antsel_avail;	/* Ant selection availability (SROM based) */
58305491d2cSKalle Valo 	struct brcms_antselcfg antcfg_11n; /* antenna configuration */
58405491d2cSKalle Valo 	struct brcms_antselcfg antcfg_cur; /* current antenna config (auto) */
58505491d2cSKalle Valo };
58605491d2cSKalle Valo 
58705491d2cSKalle Valo enum brcms_bss_type {
58805491d2cSKalle Valo 	BRCMS_TYPE_STATION,
58905491d2cSKalle Valo 	BRCMS_TYPE_AP,
59005491d2cSKalle Valo 	BRCMS_TYPE_ADHOC,
59105491d2cSKalle Valo };
59205491d2cSKalle Valo 
59305491d2cSKalle Valo /*
59405491d2cSKalle Valo  * BSS configuration state
59505491d2cSKalle Valo  *
59605491d2cSKalle Valo  * wlc: wlc to which this bsscfg belongs to.
59705491d2cSKalle Valo  * type: interface type
59805491d2cSKalle Valo  * SSID_len: the length of SSID
59905491d2cSKalle Valo  * SSID: SSID string
60005491d2cSKalle Valo  *
60105491d2cSKalle Valo  *
60205491d2cSKalle Valo  * BSSID: BSSID (associated)
60305491d2cSKalle Valo  * cur_etheraddr: h/w address
60405491d2cSKalle Valo  * flags: BSSCFG flags; see below
60505491d2cSKalle Valo  *
60605491d2cSKalle Valo  * current_bss: BSS parms in ASSOCIATED state
60705491d2cSKalle Valo  *
60805491d2cSKalle Valo  *
60905491d2cSKalle Valo  * ID: 'unique' ID of this bsscfg, assigned at bsscfg allocation
61005491d2cSKalle Valo  */
61105491d2cSKalle Valo struct brcms_bss_cfg {
61205491d2cSKalle Valo 	struct brcms_c_info *wlc;
61305491d2cSKalle Valo 	enum brcms_bss_type type;
61405491d2cSKalle Valo 	u8 SSID_len;
61505491d2cSKalle Valo 	u8 SSID[IEEE80211_MAX_SSID_LEN];
61605491d2cSKalle Valo 	u8 BSSID[ETH_ALEN];
61705491d2cSKalle Valo 	struct brcms_bss_info *current_bss;
61805491d2cSKalle Valo };
61905491d2cSKalle Valo 
62005491d2cSKalle Valo int brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p);
62105491d2cSKalle Valo int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
62205491d2cSKalle Valo 			   uint *blocks);
62305491d2cSKalle Valo 
62405491d2cSKalle Valo int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config);
62505491d2cSKalle Valo void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags);
62605491d2cSKalle Valo u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, uint mac_len);
62705491d2cSKalle Valo u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
62805491d2cSKalle Valo 			       bool use_rspec, u16 mimo_ctlchbw);
62905491d2cSKalle Valo u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
63005491d2cSKalle Valo 			       u32 rts_rate, u32 frame_rate,
63105491d2cSKalle Valo 			       u8 rts_preamble_type, u8 frame_preamble_type,
63205491d2cSKalle Valo 			       uint frame_len, bool ba);
63305491d2cSKalle Valo void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
63405491d2cSKalle Valo 			    struct ieee80211_sta *sta, void (*dma_callback_fn));
63505491d2cSKalle Valo void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend);
63605491d2cSKalle Valo int brcms_c_set_nmode(struct brcms_c_info *wlc);
63705491d2cSKalle Valo void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, u32 bcn_rate);
63805491d2cSKalle Valo void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type);
63905491d2cSKalle Valo void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
64005491d2cSKalle Valo 			  bool mute, struct txpwr_limits *txpwr);
64105491d2cSKalle Valo void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v);
64205491d2cSKalle Valo u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset);
64305491d2cSKalle Valo void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
64405491d2cSKalle Valo 		 int bands);
64505491d2cSKalle Valo void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags);
64605491d2cSKalle Valo void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val);
64705491d2cSKalle Valo void brcms_b_phy_reset(struct brcms_hardware *wlc_hw);
64805491d2cSKalle Valo void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw);
64905491d2cSKalle Valo void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw);
65005491d2cSKalle Valo void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
65105491d2cSKalle Valo 				     u32 override_bit);
65205491d2cSKalle Valo void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
65305491d2cSKalle Valo 				       u32 override_bit);
65405491d2cSKalle Valo void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset,
65505491d2cSKalle Valo 				int len, void *buf);
65605491d2cSKalle Valo u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate);
65705491d2cSKalle Valo void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
65805491d2cSKalle Valo 			   const void *buf, int len, u32 sel);
65905491d2cSKalle Valo void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset,
66005491d2cSKalle Valo 			     void *buf, int len, u32 sel);
66105491d2cSKalle Valo void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode);
66205491d2cSKalle Valo u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw);
66305491d2cSKalle Valo void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk);
66405491d2cSKalle Valo void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk);
66505491d2cSKalle Valo void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on);
66605491d2cSKalle Valo void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant);
66705491d2cSKalle Valo void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode);
66805491d2cSKalle Valo void brcms_c_init_scb(struct scb *scb);
66905491d2cSKalle Valo 
67005491d2cSKalle Valo #endif				/* _BRCM_MAIN_H_ */
671