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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 for muxing and gating Tegra's clocks, and setting their rates.
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
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H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
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H A Dsamsung,s5pv210-clock.txt9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
20 All available clocks are defined as preprocessor macros in
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
23 External clocks:
25 There are several clocks that are generated outside the SoC. It is expected
27 clock-output-names:
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H A Dclk-s5pv210-audss.txt3 The Samsung Audio Subsystem clock controller generates and supplies clocks
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
16 not specified (i.e. xusbxti is used for PLL reference), it is fixed to
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
19 - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
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H A Dsamsung,s5pv210-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 All available clocks are defined as preprocessor macros in
17 include/dt-bindings/clock/s5pv210-audss.h header.
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H A Drenesas,9series.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dsamsung,s5pv210-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
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H A Dcanaan,k210-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
24 clocks:
27 Phandle of the SoC 26MHz fixed-rate oscillator clock.
[all …]
H A Dsamsung,exynos5410-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
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H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc
[all...]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
34 clocks:
40 dma-names:
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H A Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-maste
[all...]
H A Dnvidia,tegra20-spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
35 clocks:
38 clock-names:
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqcom,ipq4019-mdio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
15 - enum:
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
19 - items:
20 - enum:
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dstratix10-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* fixed rate clocks */
15 /* fixed factor clocks */
21 /* PLL clocks */
26 /* Periph clocks */
61 /* Gate clocks */
H A Dagilex-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* fixed rate clocks */
16 /* PLL clocks */
31 /* fixed factor clocks */
45 /* Gate clocks */
H A Dmaxim,max77620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Device Tree binding constants clocks for the Maxim 77620 PMIC.
11 /* Fixed rate clocks. */
15 /* Total number of clocks. */
H A Dmaxim,max77802.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Device Tree binding constants clocks for the Maxim 77802 PMIC.
11 /* Fixed rate clocks. */
16 /* Total number of clocks. */
H A Dsamsung,s2mps11.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC.
11 /* Fixed rate clocks. */
17 /* Total number of clocks. */
H A Dmaxim,max77686.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Device Tree binding constants clocks for the Maxim 77686 PMIC.
11 /* Fixed rate clocks. */
17 /* Total number of clocks. */
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynqmp-sck-kv-g-revA.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-xgbe-b.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <250000000>;
12 clock-output-names = "xgmacclk0_dma_250mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <250000000>;
19 clock-output-names = "xgmacclk0_ptp_250mhz";
23 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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