1NVIDIA Tegra124 and Tegra132 Clock And Reset Controller 2 3This binding uses the common clock binding: 4Documentation/devicetree/bindings/clock/clock-bindings.txt 5 6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible 7for muxing and gating Tegra's clocks, and setting their rates. 8 9Required properties : 10- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" 11- reg : Should contain CAR registers location and length 12- clocks : Should contain phandle and clock specifiers for two clocks: 13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 14- #clock-cells : Should be 1. 15 In clock consumers, this cell represents the clock ID exposed by the 16 CAR. The assignments may be found in the header files 17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common 18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h> 19 (for Tegra124-specific clocks). 20- #reset-cells : Should be 1. 21 In clock consumers, this cell represents the bit number in the CAR's 22 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. 23- nvidia,external-memory-controller : phandle of the EMC driver. 24 25The node should contain a "emc-timings" subnode for each supported RAM type (see 26field RAM_CODE in register PMC_STRAPPING_OPT_A). 27 28Required properties for "emc-timings" nodes : 29- nvidia,ram-code : Should contain the value of RAM_CODE this timing set 30 is used for. 31 32Each "emc-timings" node should contain a "timing" subnode for every supported 33EMC clock rate. 34 35Required properties for "timing" nodes : 36- clock-frequency : Should contain the memory clock rate to which this timing 37relates. 38- nvidia,parent-clock-frequency : Should contain the rate at which the current 39parent of the EMC clock should be running at this timing. 40- clocks : Must contain an entry for each entry in clock-names. 41 See ../clocks/clock-bindings.txt for details. 42- clock-names : Must include the following entries: 43 - emc-parent : the clock that should be the parent of the EMC clock at this 44timing. 45 46Example SoC include file: 47 48/ { 49 tegra_car: clock@60006000 { 50 compatible = "nvidia,tegra124-car"; 51 reg = <0x60006000 0x1000>; 52 #clock-cells = <1>; 53 #reset-cells = <1>; 54 nvidia,external-memory-controller = <&emc>; 55 }; 56 57 usb@c5004000 { 58 clocks = <&tegra_car TEGRA124_CLK_USB2>; 59 }; 60}; 61 62Example board file: 63 64/ { 65 clocks { 66 compatible = "simple-bus"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 70 osc: clock@0 { 71 compatible = "fixed-clock"; 72 reg = <0>; 73 #clock-cells = <0>; 74 clock-frequency = <112400000>; 75 }; 76 77 clk_32k: clock@1 { 78 compatible = "fixed-clock"; 79 reg = <1>; 80 #clock-cells = <0>; 81 clock-frequency = <32768>; 82 }; 83 }; 84 85 &tegra_car { 86 clocks = <&clk_32k> <&osc>; 87 }; 88 89 clock@60006000 { 90 emc-timings-3 { 91 nvidia,ram-code = <3>; 92 93 timing-12750000 { 94 clock-frequency = <12750000>; 95 nvidia,parent-clock-frequency = <408000000>; 96 clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 97 clock-names = "emc-parent"; 98 }; 99 timing-20400000 { 100 clock-frequency = <20400000>; 101 nvidia,parent-clock-frequency = <408000000>; 102 clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 103 clock-names = "emc-parent"; 104 }; 105 }; 106 }; 107}; 108