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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dethernet-phy-package.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Package Common Properties
10 - Christian Marangi <ansuelsmth@gmail.com>
13 PHY packages are multi-port Ethernet PHY of the same family
14 and each Ethernet PHY is affected by the global configuration
15 of the PHY package.
17 Each reg of the PHYs defined in the PHY package node is
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H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCA807x Ethernet PHY
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
14 Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
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H A Dicplus-ip101ag.txt1 IC Plus Corp. IP101A / IP101G Ethernet PHYs
3 There are different models of the IP101G Ethernet PHY:
4 - IP101GR (32-pin QFN package)
5 - IP101G (die only, no package)
6 - IP101GA (48-pin LQFP package)
8 There are different models of the IP101A Ethernet PHY (which is the
10 - IP101A (48-pin LQFP package)
11 - IP101AH (48-pin LQFP package)
13 Optional properties for the IP101GR (32-pin QFN package):
15 - icplus,select-rx-error:
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H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/share/man/man4/
H A Dice.42 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2019-2020, Intel Corporation
40 .Nd Intel Ethernet 800 Series Driver
70 in the Intel\(rg Ethernet 800 Series.
73 .Bl -bullet -compact
75 Intel\(rg Ethernet Controller E810\-C
77 Intel\(rg Ethernet Controller E810\-XXV
79 Intel\(rg Ethernet Connection E822\-C
81 Intel\(rg Ethernet Connection E822\-L
83 Intel\(rg Ethernet Connection E823\-C
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H A Dsis.415 .\" 4. Neither the name of the author nor the names of any co-contributors
36 .Nd "SiS 900, SiS 7016 and NS DP83815/DP83816 Fast Ethernet device driver"
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
55 driver provides support for PCI Ethernet adapters and embedded
57 and SiS 7016 Fast Ethernet controller chips.
61 PCI Ethernet controller chip.
63 The SiS 900 is a 100Mbps Ethernet MAC and MII-compliant transceiver
64 in a single package.
68 that it has no internal PHY, requiring instead an external transceiver
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/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
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/freebsd/sys/arm64/conf/
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
30 options VFP # Floating-point support
69 # Microsoft Hyper-V
80 device al_pci # Annapurna Alpine PCI-E
81 options PCI_HP # PCI-Express native HotPlug
82 options PCI_IOV # PCI SR-IOV support
84 # Ethernet NICs
86 device awg # Allwinner EMAC Gigabit Ethernet
91 device al_eth # Annapurna Alpine Ethernet NIC
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc5121ads.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
17 * stacked package.
32 compatible = "cfi-flash";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 bank-width = <4>;
37 device-width = <2>;
42 read-only;
52 device-tree@3ec0000 {
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/freebsd/sys/dev/bhnd/
H A Dbhnd_ids.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 1999-2015, Broadcom Corporation
9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
30 * JEDEC JEP-106 Core Vendor IDs
32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell
38 * will need to convert bus-specific vendor IDs to their BHND_MFGID
39 * JEP-106 equivalents.
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/freebsd/sys/dev/ice/
H A Dice_lib.c1 /* SPDX-License-Identifier: BSD-3-Clause */
209 * package version comparison functions
270 * ice_map_bar - Map PCIe BAR memory
281 if (bar->res != NULL) { in ice_map_bar()
286 bar->rid = PCIR_BAR(bar_num); in ice_map_bar()
287 bar->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &bar->rid, in ice_map_bar()
289 if (!bar->res) { in ice_map_bar()
294 bar->tag = rman_get_bustag(bar->res); in ice_map_bar()
295 bar->handle = rman_get_bushandle(bar->res); in ice_map_bar()
296 bar->size = rman_get_size(bar->res); in ice_map_bar()
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H A Dice_common.c1 /* SPDX-License-Identifier: BSD-3-Clause */
127 * ice_dump_phy_type - helper function to dump phy_type
158 * ice_set_mac_type - Sets MAC type
168 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) in ice_set_mac_type()
171 switch (hw->device_id) { in ice_set_mac_type()
178 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
199 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
205 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
225 hw->mac_type = ICE_MAC_E830; in ice_set_mac_type()
228 hw->mac_type = ICE_MAC_UNKNOWN; in ice_set_mac_type()
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H A Dif_ice_iflib.c1 /* SPDX-License-Identifier: BSD-3-Clause */
272 * scctx->isc_tx_tso_size_max + the VLAN header is a valid size.
276 * DMA tag. However, scctx->isc_tx_tso_segsize_max is used to set the
305 * IFLIB_SKIP_MSIX allows the driver to handle allocating MSI-X
328 /* Static driver-wide sysctls */
332 * ice_pci_mapping - Map PCI BAR memory
343 rc = ice_map_bar(sc->dev, &sc->bar0, 0); in ice_pci_mapping()
351 * ice_free_pci_mapping - Release PCI BAR memory
360 ice_free_bar(sc->dev, &sc->bar0); in ice_free_pci_mapping()
368 * ice_register - register device method callback
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
20 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588s-odroid-m2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/usb/pd.h>
12 model = "Hardkernel ODROID-M2";
13 compatible = "hardkernel,odroid-m2", "rockchip,rk3588s";
22 stdout-path = "serial2:1500000n8";
26 compatible = "gpio-leds";
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H A Drk3588-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62x-sk-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include "k3-am625.dtsi"
27 stdout-path = "serial2:115200n8";
31 bootph-pre-ram;
37 reserved-memory {
38 #address-cells = <2>;
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/freebsd/sys/dev/axgbe/
H A Dif_axgbe_pci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
54 #include "xgbe-common.h"
138 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
144 { -1, 0 }
149 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
150 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
317 axgbe_miibus_readreg(device_t dev, int phy, int reg) in axgbe_miibus_readreg() argument
320 struct xgbe_prv_data *pdata = &sc->pdata; in axgbe_miibus_readreg()
323 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg); in axgbe_miibus_readreg()
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/freebsd/share/misc/
H A Dusb_vendors6 # http://www.linux-usb.org/usb-ids.html
7 # or send entries as patches (diff -u old new) in the
10 # http://www.linux-usb.org/usb.ids
13 # Date: 2025-07-26 20:34:01
20 # device device_name <-- single tab
21 # interface interface_name <-- two tabs
38 5301 GW-US54ZGL 802.11bg
54 145f NW-3100 802.11b/g 54Mbps Wireless Network Adapter [zd1211]
64 0200 TP-Link
86 120e ASI120MC-S Planetary Camera
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dnvm_cfg.h2 * Copyright (c) 2017-2018 Cavium, Inc.
33 * Description: NVM config file - Generated file from nvm cfg excel.
511 /* Select package id method */
527 /* Max MSIX for Ethernet in default mode */
556 /* GPIO which triggers run-time port swap according to the map
604 /* Enable option 195 - Overriding the PCIe Preset value */
609 /* PCIe Preset value - applies only if option 194 is enabled */
612 /* Port mapping to be used when the run-time GPIO for port-swap is
629 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event
855 /* Set NC-SI package ID */
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H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd/sys/dev/ixl/
H A Di40e_type.h3 Copyright (c) 2013-2018, Intel Corporation
68 /* Max timeout in ms for the phy to respond */
105 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
106 (R)->next_to_clean - (R)->next_to_use - 1)
113 /* debug masks - set these bits in hw->debug_mask to control output */
275 /* 2nd byte: ethernet compliance codes for 10/40G */
284 /* 3rd byte: ethernet compliance codes for 1G */
296 /* all the phy types the NVM is capable of */
331 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
373 * Mode2: Filter for non-tunneled traffic
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/freebsd/sys/dev/bnxt/bnxt_en/
H A Dhsi_struct_def.h1 /*-
34 * Copyright(c) 2001-2025, Broadcom. All rights reserved. The
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
122 /* Engine CKV - The Alias key EC curve and ECC public key information. */
124 /* Engine CKV - Initialization vector. */
126 /* Engine CKV - Authentication tag. */
128 /* Engine CKV - The encrypted data. */
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