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Searched full:esync (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Ddpll.c65 * Supported esync ranges for input and for output per output pair type
127 struct dpll_pin_esync *esync, in zl3073x_dpll_input_pin_esync_get() argument
142 esync->range = esync_freq_ranges; in zl3073x_dpll_input_pin_esync_get()
143 esync->range_num = ARRAY_SIZE(esync_freq_ranges); in zl3073x_dpll_input_pin_esync_get()
147 esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; in zl3073x_dpll_input_pin_esync_get()
148 esync->pulse = 25; in zl3073x_dpll_input_pin_esync_get()
151 esync->freq = 0; in zl3073x_dpll_input_pin_esync_get()
152 esync->pulse = 0; in zl3073x_dpll_input_pin_esync_get()
175 /* Use freq == 0 to disable esync */ in zl3073x_dpll_input_pin_esync_set()
694 struct dpll_pin_esync *esync, in zl3073x_dpll_output_pin_esync_get() argument
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H A Dprop.c180 * board label, connection type, supported frequencies and esync capability
265 "esync-control"); in zl3073x_pin_props_get()
H A Dref.c129 /* Read eSync and N-div rated registers */ in zl3073x_ref_state_fetch()
/linux/drivers/dpll/
H A Ddpll_netlink.c502 struct dpll_pin_esync esync; in dpll_msg_add_pin_esync() local
509 dpll_priv(dpll), &esync, extack); in dpll_msg_add_pin_esync()
514 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), in dpll_msg_add_pin_esync()
515 &esync.freq, DPLL_A_PIN_PAD)) in dpll_msg_add_pin_esync()
517 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) in dpll_msg_add_pin_esync()
519 for (i = 0; i < esync.range_num; i++) { in dpll_msg_add_pin_esync()
525 sizeof(esync.range[i].min), in dpll_msg_add_pin_esync()
526 &esync.range[i].min, DPLL_A_PIN_PAD)) in dpll_msg_add_pin_esync()
529 sizeof(esync.range[i].max), in dpll_msg_add_pin_esync()
530 &esync.range[i].max, DPLL_A_PIN_PAD)) in dpll_msg_add_pin_esync()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c2104 * @esync: on success holds embedded sync pin properties
2118 struct dpll_pin_esync *esync, in ice_dpll_output_esync_get() argument
2133 esync->range = ice_esync_range; in ice_dpll_output_esync_get()
2134 esync->range_num = ARRAY_SIZE(ice_esync_range); in ice_dpll_output_esync_get()
2136 esync->freq = DPLL_PIN_FREQUENCY_1_HZ; in ice_dpll_output_esync_get()
2137 esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; in ice_dpll_output_esync_get()
2139 esync->freq = 0; in ice_dpll_output_esync_get()
2140 esync->pulse = 0; in ice_dpll_output_esync_get()
2208 * @esync: on success holds embedded sync pin properties
2222 struct dpll_pin_esync *esync, in ice_dpll_input_esync_get() argument
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8750-mdss.yaml230 "esync",
336 "esync",
/linux/include/linux/
H A Ddpll.h128 struct dpll_pin_esync *esync,
/linux/arch/xtensa/kernel/
H A Dentry.S1714 esync
1887 esync
/linux/sound/pci/echoaudio/
H A Dechoaudio.c1516 "Internal", "Word", "Super", "S/PDIF", "ADAT", "ESync", in snd_echo_clock_source_info()
/linux/arch/powerpc/xmon/
H A Dppc-opc.c687 /* The ESYNC field in an X (sync) form instruction. */
688 #define ESYNC STRM + 1 macro
692 #define SV ESYNC + 1
1528 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1529 the complement of ESYNC-bit2. */
5847 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},