58  * Supported esync ranges for input and for output per output pair type
160 				 struct dpll_pin_esync *esync,  in zl3073x_dpll_input_pin_esync_get()  argument
189 	/* Get esync divisor */  in zl3073x_dpll_input_pin_esync_get()
198 		esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0;  in zl3073x_dpll_input_pin_esync_get()
199 		esync->pulse = 25;  in zl3073x_dpll_input_pin_esync_get()
202 		esync->freq = 0;  in zl3073x_dpll_input_pin_esync_get()
203 		esync->pulse = 0;  in zl3073x_dpll_input_pin_esync_get()
207 	/* If the pin supports esync control expose its range but only  in zl3073x_dpll_input_pin_esync_get()
211 		esync->range = esync_freq_ranges;  in zl3073x_dpll_input_pin_esync_get()
212 		esync->range_num = ARRAY_SIZE(esync_freq_ranges);  in zl3073x_dpll_input_pin_esync_get()
214 		esync->range = NULL;  in zl3073x_dpll_input_pin_esync_get()
215 		esync->range_num = 0;  in zl3073x_dpll_input_pin_esync_get()
248 	/* Use freq == 0 to disable esync */  in zl3073x_dpll_input_pin_esync_set()
948 				  struct dpll_pin_esync *esync,  in zl3073x_dpll_output_pin_esync_get()  argument
964 	/* If N-division is enabled, esync is not supported. The register used  in zl3073x_dpll_output_pin_esync_get()
965 	 * for N-division is also used for the esync divider so both cannot  in zl3073x_dpll_output_pin_esync_get()
1009 		/* No need to read esync data if it is not enabled */  in zl3073x_dpll_output_pin_esync_get()
1010 		esync->freq = 0;  in zl3073x_dpll_output_pin_esync_get()
1011 		esync->pulse = 0;  in zl3073x_dpll_output_pin_esync_get()
1016 	/* Read esync period */  in zl3073x_dpll_output_pin_esync_get()
1021 	/* Check esync divisor for zero */  in zl3073x_dpll_output_pin_esync_get()
1023 		dev_err(dev, "Zero esync divisor for OUTPUT%u got from device\n",  in zl3073x_dpll_output_pin_esync_get()
1028 	/* Get esync pulse width in units of half synth cycles */  in zl3073x_dpll_output_pin_esync_get()
1033 	/* Compute esync frequency */  in zl3073x_dpll_output_pin_esync_get()
1034 	esync->freq = synth_freq / output_div / esync_period;  in zl3073x_dpll_output_pin_esync_get()
1037 	 * the esync pulse percentage can be determined.  in zl3073x_dpll_output_pin_esync_get()
1041 	esync->pulse = (50 * esync_width) / output_div;  in zl3073x_dpll_output_pin_esync_get()
1044 	/* Set supported esync ranges if the pin supports esync control and  in zl3073x_dpll_output_pin_esync_get()
1048 		esync->range = esync_freq_ranges;  in zl3073x_dpll_output_pin_esync_get()
1049 		esync->range_num = ARRAY_SIZE(esync_freq_ranges);  in zl3073x_dpll_output_pin_esync_get()
1051 		esync->range = NULL;  in zl3073x_dpll_output_pin_esync_get()
1052 		esync->range_num = 0;  in zl3073x_dpll_output_pin_esync_get()
1075 	/* If N-division is enabled, esync is not supported. The register used  in zl3073x_dpll_output_pin_esync_set()
1076 	 * for N-division is also used for the esync divider so both cannot  in zl3073x_dpll_output_pin_esync_set()
1113 	/* If esync is being disabled just write mailbox and finish */  in zl3073x_dpll_output_pin_esync_set()
1134 	/* Compute and update esync period */  in zl3073x_dpll_output_pin_esync_set()
1141 	 * the output_div. To get the supported esync pulse width of 25% of the  in zl3073x_dpll_output_pin_esync_set()
1312 	/* Get N-pin divisor (shares the same register with esync */  in zl3073x_dpll_output_pin_frequency_set()
1706 	/* Save package label & esync capability */  in zl3073x_dpll_pin_register()