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/linux/drivers/net/ethernet/brocade/bna/
H A Dbna_enet.c17 if (ethport->bna->enet.type == BNA_ENET_T_REGULAR) in ethport_can_be_up()
150 bna_bfi_pause_set_rsp(struct bna_enet *enet, struct bfi_msgq_mhdr *msghdr) in bna_bfi_pause_set_rsp() argument
152 bfa_fsm_send_event(enet, ENET_E_FWRESP_PAUSE); in bna_bfi_pause_set_rsp()
342 bna_bfi_pause_set_rsp(&bna->enet, msghdr); in bna_msgq_rsp_handler()
390 cbfn(&(_ethport)->bna->enet); \
448 lpbk_up_req->mode = (ethport->bna->enet.type == in bna_bfi_ethport_lpbk_up()
479 if (ethport->bna->enet.type == BNA_ENET_T_REGULAR) in bna_bfi_ethport_up()
488 if (ethport->bna->enet.type == BNA_ENET_T_REGULAR) in bna_bfi_ethport_down()
753 bna_enet_cb_ethport_stopped(struct bna_enet *enet) in bna_enet_cb_ethport_stopped() argument
755 bfa_wc_down(&enet->chld_stop_wc); in bna_enet_cb_ethport_stopped()
[all …]
H A Dbna.h300 /* APIs for ENET */
337 /* APIs for ENET */
375 /* ENET */
378 int bna_enet_mtu_get(struct bna_enet *enet);
381 void bna_enet_cb_tx_stopped(struct bna_enet *enet);
382 void bna_enet_cb_rx_stopped(struct bna_enet *enet);
385 void bna_enet_enable(struct bna_enet *enet);
386 void bna_enet_disable(struct bna_enet *enet, enum bna_cleanup_type type,
388 void bna_enet_pause_config(struct bna_enet *enet,
390 void bna_enet_mtu_set(struct bna_enet *enet, int mtu,
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,cpm-enet.yaml4 $id: http://devicetree.org/schemas/net/fsl,cpm-enet.yaml#
7 title: Network for cpm enet
16 - fsl,cpm1-scc-enet
17 - fsl,cpm2-scc-enet
18 - fsl,cpm1-fec-enet
19 - fsl,cpm2-fcc-enet
20 - fsl,qe-enet
23 - fsl,mpc8272-fcc-enet
24 - const: fsl,cpm2-fcc-enet
50 compatible = "fsl,mpc8272-fcc-enet",
[all …]
H A Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
26 compatible = "ni,xge-enet-3.00";
51 compatible = "ni,xge-enet-2.00";
67 compatible = "ni,xge-enet-2.00";
H A Dezchip_enet.txt4 - compatible: Should be "ezchip,nps-mgt-enet"
6 - interrupts: Should contain the ENET interrupt
11 compatible = "ezchip,nps-mgt-enet";
H A Dbrcm,bcm4908-enet.yaml4 $id: http://devicetree.org/schemas/net/brcm,bcm4908-enet.yaml#
19 const: brcm,bcm4908-enet
49 compatible = "brcm,bcm4908-enet";
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h154 * struct nps_enet_priv - Storage of ENET's private information.
155 * @regs_base: Base address of ENET memory-mapped control registers.
170 * nps_enet_reg_set - Sets ENET register with provided value.
171 * @priv: Pointer to EZchip ENET private data structure.
182 * nps_enet_reg_get - Gets value of specified ENET register.
183 * @priv: Pointer to EZchip ENET private data structure.
/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c144 [FUNC_ENET] = "enet",
240 LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
241 LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
257 LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
258 LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
259 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
260 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
261 LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
262 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
263 LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
[all …]
/linux/drivers/net/ethernet/apm/xgene-v2/
H A DMakefile6 xgene-enet-v2-objs := main.o mac.o enet.o ring.o mdio.o ethtool.o
7 obj-$(CONFIG_NET_XGENE_V2) += xgene-enet-v2.o
/linux/arch/powerpc/boot/dts/
H A Dmpc885ads.dts98 compatible = "fsl,mpc885-fec-enet",
99 "fsl,pq1-fec-enet";
110 compatible = "fsl,mpc885-fec-enet",
111 "fsl,pq1-fec-enet";
201 compatible = "fsl,mpc885-scc-enet",
202 "fsl,cpm1-scc-enet";
H A Dadder875-redboot.dts95 compatible = "fsl,mpc875-fec-enet",
96 "fsl,pq1-fec-enet";
107 compatible = "fsl,mpc875-fec-enet",
108 "fsl,pq1-fec-enet";
H A Dadder875-uboot.dts94 compatible = "fsl,mpc875-fec-enet",
95 "fsl,pq1-fec-enet";
106 compatible = "fsl,mpc875-fec-enet",
107 "fsl,pq1-fec-enet";
H A Dep8248e.dts156 compatible = "fsl,mpc8248-fcc-enet",
157 "fsl,cpm2-fcc-enet";
169 compatible = "fsl,mpc8248-fcc-enet",
170 "fsl,cpm2-fcc-enet";
H A Dtqm8xx.dts111 compatible = "fsl,mpc866-fec-enet",
112 "fsl,pq1-fec-enet";
181 compatible = "fsl,mpc860-scc-enet",
182 "fsl,cpm1-scc-enet";
H A Dmpc866ads.dts78 compatible = "fsl,mpc866-fec-enet",
79 "fsl,pq1-fec-enet";
160 compatible = "fsl,mpc866-scc-enet",
161 "fsl,cpm1-scc-enet";
H A Dep88xc.dts93 compatible = "fsl,mpc885-fec-enet",
94 "fsl,pq1-fec-enet";
105 compatible = "fsl,mpc885-fec-enet",
106 "fsl,pq1-fec-enet";
H A Dmgcoge.dts148 compatible = "fsl,mpc8247-scc-enet",
149 "fsl,cpm2-scc-enet";
190 compatible = "fsl,cpm2-fcc-enet";
203 compatible = "fsl,cpm2-fcc-enet";
/linux/drivers/clk/mxs/
H A Dclk-imx28.c38 #define ENET (CLKCTRL + 0x0140) macro
87 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init()
102 val = readl_relaxed(ENET); in clk_misc_init()
104 writel_relaxed(val, ENET); in clk_misc_init()
189 clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels)); in mx28_clocks_init()
203 clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27); in mx28_clocks_init()
224 clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); in mx28_clocks_init()
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); in mx28_clocks_init()
/linux/arch/mips/bcm63xx/
H A Dclk.c433 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
434 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
462 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
476 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
490 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc),
491 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc),
509 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0),
510 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1),
/linux/arch/sparc/include/asm/
H A Ddma.h41 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
55 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
56 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
57 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
/linux/drivers/net/ethernet/apm/xgene/
H A DMakefile6 xgene-enet-objs := xgene_enet_hw.o xgene_enet_sgmac.o xgene_enet_xgmac.o \
9 obj-$(CONFIG_NET_XGENE) += xgene-enet.o
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm-usxgmii-exp1-exp2.dtso3 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
4 * and ENET-2 Expansion slots of J784S4 EVM.
/linux/arch/mips/boot/dts/img/
H A Dpistachio_marduk.dts19 ethernet0 = &enet;
107 &enet {
/linux/arch/mips/ath25/
H A Dar5312_regs.h40 * The AR5312 supports 2 enet MACS, even though many reference boards only
41 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
42 * PHY or PHY switch. The AR2312 supports 1 enet MAC.
/linux/drivers/net/ethernet/broadcom/
H A Db44.h52 #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */
53 #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */
54 #define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */
55 #define B44_FILT_DATA 0x0094UL /* ENET Filter Data */
173 #define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */

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