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/linux/arch/loongarch/kvm/intc/
H A Deiointc.c167 struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc; in kvm_eiointc_read() local
169 if (!eiointc) { in kvm_eiointc_read()
170 kvm_err("%s: eiointc irqchip not valid!\n", __func__); in kvm_eiointc_read()
175 kvm_err("%s: eiointc not aligned addr %llx len %d\n", __func__, addr, len); in kvm_eiointc_read()
182 spin_lock_irqsave(&eiointc->lock, flags); in kvm_eiointc_read()
183 ret = loongarch_eiointc_read(vcpu, eiointc, addr, &data); in kvm_eiointc_read()
184 spin_unlock_irqrestore(&eiointc->lock, flags); in kvm_eiointc_read()
303 struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc; in kvm_eiointc_write() local
305 if (!eiointc) { in kvm_eiointc_write()
306 kvm_err("%s: eiointc irqchip not valid!\n", __func__); in kvm_eiointc_write()
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi90 interrupt-parent = <&eiointc>;
100 interrupt-parent = <&eiointc>;
110 interrupt-parent = <&eiointc>;
120 interrupt-parent = <&eiointc>;
163 eiointc: interrupt-controller@1fe11600 { label
164 compatible = "loongson,ls2k0500-eiointc";
353 interrupt-parent = <&eiointc>;
361 interrupt-parent = <&eiointc>;
369 interrupt-parent = <&eiointc>;
386 interrupt-parent = <&eiointc>;
[all …]
H A Dloongson-2k2000.dtsi96 interrupt-parent = <&eiointc>;
139 eiointc: interrupt-controller@1fe01600 { label
140 compatible = "loongson,ls2k2000-eiointc";
154 interrupt-parent = <&eiointc>;
165 interrupt-parent = <&eiointc>;
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,eiointc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,eiointc.yaml#
23 - loongson,ls2k0500-eiointc
24 - loongson,ls2k2000-eiointc
48 eiointc: interrupt-controller@1fe11600 {
49 compatible = "loongson,ls2k0500-eiointc";
/linux/drivers/irqchip/
H A Dirq-loongson-eiointc.c8 #define pr_fmt(fmt) "eiointc: " fmt
212 /* Enable cpu interrupt pin from eiointc */ in eiointc_router_init()
296 * eiointc interrupt controller routes to different cpu interrupt pins in eiointc_irq_dispatch()
339 .name = "EIOINTC",
515 * Only the first eiointc device on VM supports routing to in eiointc_init()
516 * different CPU interrupt pins. The later eiointc devices use in eiointc_init()
517 * generic method if there are multiple eiointc devices in future in eiointc_init()
545 "irqchip/loongarch/eiointc:starting", in eiointc_init()
632 if (of_device_is_compatible(of_node, "loongson,ls2k0500-eiointc")) in eiointc_of_init()
651 IRQCHIP_DECLARE(loongson_ls2k0500_eiointc, "loongson,ls2k0500-eiointc", eiointc_of_init);
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/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst14 Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、
18 CPUINTC是一種CPU內部的每個核本地的中斷控制器，LIOINTC/EIOINTC/HTVECINTC是CPU內部的
72 | EIOINTC | | LIOINTC | <-- | UARTs |
105 EIOINTC::
154 - EIOINTC：即《龍芯3A5000處理器使用手冊》第11.2節所描述的“擴展I/O中斷”；
/linux/arch/loongarch/kernel/
H A Dacpi.c141 struct acpi_madt_eio_pic *eiointc = NULL; in acpi_parse_eio_master() local
143 eiointc = (struct acpi_madt_eio_pic *)header; in acpi_parse_eio_master()
144 if (BAD_MADT_ENTRY(eiointc, end)) in acpi_parse_eio_master()
147 core = eiointc->node * CORES_PER_EIO_NODE; in acpi_parse_eio_master()
/linux/arch/loongarch/kvm/
H A DMakefile20 kvm-y += intc/eiointc.o
H A Dmain.c404 /* Register LoongArch EIOINTC interrupt controller interface. */ in kvm_loongarch_env_init()
/linux/arch/loongarch/include/asm/
H A Dkvm_host.h99 * For eiointc interrupt controller, max destination CPUID size is 256
133 struct loongarch_eiointc *eiointc; member