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/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
23 reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dimg,pdc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - James Hogan <jhogan@kernel.org>
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
28 <1st-cell>: The interrupt-number that identifies the interrupt source.
29 0-7: Peripheral interrupts
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H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
18 to be driven per N output. An Interrupt Router can either handle edge
19 triggered or level triggered interrupts and that is fixed in hardware.
22 +----------------------+
24 +-------+ | +------+ +-----+ |
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H A Darm,gic-v5-iwb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
24 - $ref: /schemas/interrupt-controller.yaml#
28 const: arm,gic-v5-iwb
32 - description: IWB control frame
34 "#address-cells":
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H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/linux/arch/loongarch/kvm/intc/
H A Dpch_pic.c1 // SPDX-License-Identifier: GPL-2.0
21 if (mask & s->irr & ~s->mask) { in pch_pic_update_irq()
22 s->isr |= mask; in pch_pic_update_irq()
23 irq = s->htmsi_vector[irq]; in pch_pic_update_irq()
24 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
27 if (mask & s->isr & ~s->irr) { in pch_pic_update_irq()
28 s->isr &= ~mask; in pch_pic_update_irq()
29 irq = s->htmsi_vector[irq]; in pch_pic_update_irq()
30 eiointc_set_irq(s->kvm->arch.eiointc, irq, level); in pch_pic_update_irq()
50 /* called when a irq is triggered in pch pic */
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/linux/arch/m68k/coldfire/
H A Dintc-2.c2 * intc-2.c
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
10 * The external 7 fixed interrupts are part of the Edge Port unit of these
11 * ColdFire parts. They can be configured as level or edge triggered.
13 * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
37 * The EDGE Port interrupts are the fixed 7 external interrupts.
41 #define EINT1 65 /* EDGE Port interrupt 1 */
42 #define EINT7 71 /* EDGE Port interrupt 7 */
52 unsigned int irq = d->irq - MCFINT_VECBASE; in intc_irq_mask()
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H A Dintc-5272.c2 * intc.c -- interrupt controller or ColdFire 5272 SoC
24 * ColdFire interrupt controller - it truly is completely different.
34 * Note that the external interrupts are edge triggered (unlike the
35 * internal interrupt sources which are level triggered). Which means
44 static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
83 unsigned int irq = d->irq; in intc_irq_mask()
87 irq -= MCFINT_VECBASE; in intc_irq_mask()
95 unsigned int irq = d->irq; in intc_irq_unmask()
99 irq -= MCFINT_VECBASE; in intc_irq_unmask()
107 unsigned int irq = d->irq; in intc_irq_ack()
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/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
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/linux/arch/mips/include/asm/
H A Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
29 /* For read-only shared registers */
34 /* For read-write shared registers */
39 /* For read-only local registers */
44 /* For read-write local registers */
49 /* For read-only shared per-interrupt registers */
62 /* For read-write shared per-interrupt registers */
81 /* For read-only local per-interrupt registers */
88 /* For read-write local per-interrupt registers */
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
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H A Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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/linux/drivers/comedi/drivers/
H A Dpcmmio.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for Winsystems PC-104 based multifunction IO board.
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: A driver for the PCM-MIO multifunction board
13 * Devices: [Winsystems] PCM-MIO (pcmmio)
15 * Updated: Wed, May 16 2007 16:21:10 -0500
18 * A driver for the PCM-MIO multifunction board from Winsystems. This
19 * is a PC-104 based I/O board. It contains four subdevices:
21 * subdevice 0 - 16 channels of 16-bit AI
22 * subdevice 1 - 8 channels of 16-bit AO
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/linux/Documentation/devicetree/bindings/gpio/
H A Drealtek,rtd-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/realtek,rtd-gpio.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Tzuyi Chang <tychang@realtek.com>
15 RTD series SoC family, which are high-definition media processor SoCs.
20 - realtek,rtd1295-misc-gpio
21 - realtek,rtd1295-iso-gpio
22 - realtek,rtd1315e-iso-gpio
23 - realtek,rtd1319-iso-gpio
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H A Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
[all …]
H A Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
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/linux/arch/mips/sgi-ip32/
H A Dip32-irq.c31 #include "ip32-common.h"
36 crime->control; in flush_crime_bus()
41 mace->perif.ctrl.misc; in flush_mace_bus()
47 * IP0 -> software (ignored)
48 * IP1 -> software (ignored)
49 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
50 * IP3 -> (irq1) X unknown
51 * IP4 -> (irq2) X unknown
52 * IP5 -> (irq3) X unknown
53 * IP6 -> (irq4) X unknown
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-power.json34 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
44 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
54 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
64 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
132 …ry Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase she…
136 "BriefDescription": "Package C State Residency - C0",
142 …ge C State Residency - C0 : Counts the number of cycles when the package was in C0. This event ca…
146 "BriefDescription": "Package C State Residency - C2E",
152 …e C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event c…
156 "BriefDescription": "Package C State Residency - C3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-power.json36 "PublicDescription": "Cycles spent in phase-shedding power state 0",
46 "PublicDescription": "Cycles spent in phase-shedding power state 1",
56 "PublicDescription": "Cycles spent in phase-shedding power state 2",
66 "PublicDescription": "Cycles spent in phase-shedding power state 3",
125 …"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding…
129 "BriefDescription": "Package C State Residency - C0",
135 …s when the package was in C0. This event can be used in conjunction with edge detect to count C0 …
139 "BriefDescription": "Package C State Residency - C2E",
145 … when the package was in C2E. This event can be used in conjunction with edge detect to count C2E…
149 "BriefDescription": "Package C State Residency - C3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-power.json36 "PublicDescription": "Cycles spent in phase-shedding power state 0",
46 "PublicDescription": "Cycles spent in phase-shedding power state 1",
56 "PublicDescription": "Cycles spent in phase-shedding power state 2",
66 "PublicDescription": "Cycles spent in phase-shedding power state 3",
125 …"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding…
129 "BriefDescription": "Package C State Residency - C0",
135 …s when the package was in C0. This event can be used in conjunction with edge detect to count C0 …
139 "BriefDescription": "Package C State Residency - C2E",
145 … when the package was in C2E. This event can be used in conjunction with edge detect to count C2E…
149 "BriefDescription": "Package C State Residency - C3",
[all …]
/linux/arch/x86/kvm/
H A Dioapic.c7 * 75002 Paris - France
8 * http://www.linux-mandrake.com/
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
62 switch (ioapic->ioregsel) { in ioapic_read_indirect()
64 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16) in ioapic_read_indirect()
70 result = ((ioapic->id & 0xf) << 24); in ioapic_read_indirect()
75 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1; in ioapic_read_indirect()
82 redir_content = ioapic->redirtbl[index].bits; in ioapic_read_indirect()
85 result = (ioapic->ioregsel & 0x1) ? in ioapic_read_indirect()
97 ioapic->rtc_status.pending_eoi = 0; in rtc_irq_eoi_tracking_reset()
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/linux/arch/x86/kernel/apic/
H A Dio_apic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
[all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-power.json35 "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0",
45 "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1",
55 "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2",
65 "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3",
133 …ry Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase she…
137 "BriefDescription": "Package C State Residency - C0",
143 …ge C State Residency - C0 : Counts the number of cycles when the package was in C0. This event ca…
147 "BriefDescription": "Package C State Residency - C2E",
153 …e C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event c…
157 "BriefDescription": "Package C State Residency - C3",
[all …]
/linux/Documentation/devicetree/bindings/net/nfc/
H A Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux/Documentation/virt/kvm/devices/
H A Dmpic.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
38 edge, and writing 0 is ignored. Reading returns 1 if a previously
39 signaled edge has not been acknowledged, and 0 otherwise.
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