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/linux/drivers/clk/
H A Dclk-vt8500.c457 int div1, div2; in wm8750_find_pll_bits() local
464 for (div2 = 7; div2 >= 0; div2--) in wm8750_find_pll_bits()
466 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
475 *divisor2 = div2; in wm8750_find_pll_bits()
483 *divisor2 = div2; in wm8750_find_pll_bits()
505 int div1, div2; in wm8850_find_pll_bits() local
512 for (div2 = 3; div2 >= 0; div2--) in wm8850_find_pll_bits()
515 ((div1 + 1) * (1 << div2)); in wm8850_find_pll_bits()
523 *divisor2 = div2; in wm8850_find_pll_bits()
531 *divisor2 = div2; in wm8850_find_pll_bits()
[all …]
H A Dclk-npcm8xx.c327 return dev_err_probe(dev, PTR_ERR(hw), "Can't register pll2 div2\n"); in npcm8xx_clk_probe()
332 return dev_err_probe(dev, PTR_ERR(hw), "Can't register gfx div2\n"); in npcm8xx_clk_probe()
357 return dev_err_probe(dev, PTR_ERR(hw), "Can't register pre clk div2\n"); in npcm8xx_clk_probe()
362 return dev_err_probe(dev, PTR_ERR(hw), "Can't register axi div2\n"); in npcm8xx_clk_probe()
367 return dev_err_probe(dev, PTR_ERR(hw), "Can't register atb div2\n"); in npcm8xx_clk_probe()
/linux/drivers/clk/socfpga/
H A Dclk-agilex.c17 { .fw_name = "cb-intosc-hs-div2-clk",
18 .name = "cb-intosc-hs-div2-clk", },
26 { .fw_name = "cb-intosc-hs-div2-clk",
27 .name = "cb-intosc-hs-div2-clk", },
37 { .fw_name = "cb-intosc-hs-div2-clk",
38 .name = "cb-intosc-hs-div2-clk", },
50 { .fw_name = "cb-intosc-hs-div2-clk",
51 .name = "cb-intosc-hs-div2-clk", },
63 { .fw_name = "cb-intosc-hs-div2-clk",
64 .name = "cb-intosc-hs-div2-clk", },
[all …]
H A Dclk-s10.c17 { .fw_name = "cb-intosc-hs-div2-clk",
18 .name = "cb-intosc-hs-div2-clk" },
30 { .fw_name = "cb-intosc-hs-div2-clk",
31 .name = "cb-intosc-hs-div2-clk", },
39 { .fw_name = "cb-intosc-hs-div2-clk",
40 .name = "cb-intosc-hs-div2-clk" },
50 { .fw_name = "cb-intosc-hs-div2-clk",
51 .name = "cb-intosc-hs-div2-clk", },
140 { .fw_name = "cb-intosc-hs-div2-clk",
141 .name = "cb-intosc-hs-div2-clk", },
/linux/drivers/clk/uniphier/
H A Dclk-uniphier.h114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
116 UNIPHIER_CLK_DIV(parent, div2)
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
120 UNIPHIER_CLK_DIV2(parent, div2, div3)
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml171 clock-output-names = "pll0", "pll0-div2";
179 clock-output-names = "pll1", "pll1-div2";
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
205 clock-output-names = "platform-pll", "platform-pll-div2";
/linux/drivers/clk/tegra/
H A Dclk-tegra-super-cclk.c54 unsigned int div2; in cclk_super_recalc_rate() local
58 div2 = 1; in cclk_super_recalc_rate()
60 div2 = 0; in cclk_super_recalc_rate()
63 return parent_rate >> div2; in cclk_super_recalc_rate()
65 return tegra_clk_super_ops.recalc_rate(hw, parent_rate) >> div2; in cclk_super_recalc_rate()
181 * PLLX+->+-->+------------>+1| +->+ I +->+1| +->+ DIV2 +->+1| in tegra_clk_register_super_cclk()
191 * thermal DIV2 skipper. in tegra_clk_register_super_cclk()
/linux/arch/microblaze/lib/
H A Ddivsi3.S38 blti r5, div2 /* this traps r5 == 0x80000000 */
43 div2: label
56 bri div2 /* div2 */
H A Dumodsi3.S54 blti r5, div2
59 div2: label
72 bri div2 /* div2 */
H A Dudivsi3.S52 blti r5, div2
57 div2: label
70 bri div2 /* div2 */
H A Dmodsi3.S43 div2: label
56 bri div2 /* div2 */
/linux/drivers/video/fbdev/
H A Dplatinumfb.h69 #define DIV2 0x20 macro
107 {{ 26, 0 + DIV2 }, { 42, 6 }}
119 {{ 54, 3 + DIV2 }, { 67, 12 }}
131 {{ 20, 0 + DIV2 }, { 11, 2 }}
143 {{ 19, 0 + DIV2 }, { 110, 21 }}
155 {{ 71, 6 + DIV2 }, { 118, 13 + DIV2 }}
169 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}
181 {{ 122, 7 + DIV4 }, { 62, 9 + DIV2 }}
193 {{ 26, 0 + DIV4 }, { 42, 6 + DIV2 }}
241 {{ 30, 0 + DIV4 }, { 56, 7 + DIV2 }}
/linux/drivers/media/tuners/
H A Dmt2131.c89 u32 div1, num1, div2, num2; in mt2131_set_params() local
109 /* Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) */ in mt2131_set_params()
111 div2 = num2 / 8192; in mt2131_set_params()
140 b[6] = div2; in mt2131_set_params()
145 dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n", in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
H A Dmt2060.c117 // LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49
196 u32 div1,num1,div2,num2; in mt2060_set_params() local
231 // Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) in mt2060_set_params()
233 div2 = num2 / 8192; in mt2060_set_params()
252 b[5] = ((num2 >>12) & 1) | (div2 << 1); in mt2060_set_params()
256 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); in mt2060_set_params()
H A Dmt2060_priv.h26 05 | [ DIV2 ] |NUM2(12)| RW = 0x93
43 NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details )
/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c63 static int div2[] = { 1, 2, 3, 4, 6, 8, 12 }; variable
66 .divisors = div2,
67 .nr_divisors = ARRAY_SIZE(div2),
80 /* The mask field specifies the div2 entries that are valid */
H A Dclock-sh7269.c91 static int div2[] = { 1, 2, 0, 4 }; variable
94 .divisors = div2,
95 .nr_divisors = ARRAY_SIZE(div2),
108 /* The mask field specifies the div2 entries that are valid */
/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7757.c48 static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, variable
52 .divisors = div2,
53 .nr_divisors = ARRAY_SIZE(div2),
H A Dclock-shx3.c47 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
51 .divisors = div2,
52 .nr_divisors = ARRAY_SIZE(div2),
H A Dclock-sh7785.c51 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
H A Dclock-sh7786.c53 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
57 .divisors = div2,
58 .nr_divisors = ARRAY_SIZE(div2),
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dga102.c89 u32 div2 = 0; in ga102_sor_clock() local
93 div2 = 1; in ga102_sor_clock()
97 nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2); in ga102_sor_clock()
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c174 * postdiv1_2[0] = {2, 4, 8}, where div1 = 2, div2 = 4 , div1 * div2 = 8
217 /* tmp0 is POSTDIV1*POSTDIV2, now we calculate div1 and div2 value */ in sg2042_pll_get_postdiv_1_2()
219 /* (div1 * div2) <= 7, no need to use array search */ in sg2042_pll_get_postdiv_1_2()
225 /* (div1 * div2) > 7, use array search */ in sg2042_pll_get_postdiv_1_2()
H A Dclk-sg2044-pll.c173 unsigned int div1, div2; in sg2042_pll_compute_postdiv() local
177 for_each_pll_limit_range(div2, &limits[PLL_LIMIT_POSTDIV2]) { in sg2042_pll_compute_postdiv()
181 div1, div2); in sg2042_pll_compute_postdiv()
188 best_div2 = div2; in sg2042_pll_compute_postdiv()
/linux/sound/soc/codecs/
H A Dwm8737.h115 #define WM8737_DIV2 0x0080 /* DIV2 */
116 #define WM8737_DIV2_MASK 0x0080 /* DIV2 */
117 #define WM8737_DIV2_SHIFT 7 /* DIV2 */
118 #define WM8737_DIV2_WIDTH 1 /* DIV2 */

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