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/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-am654.yaml109 ti,otap-del-sel-ddr52:
110 description: Output tap delay for eMMC DDR52 timing
167 ti,itap-del-sel-ddr52:
168 description: Input tap delay for MMC DDR52 timing
234 ti,otap-del-sel-ddr52 = <0x5>;
239 ti,itap-del-sel-ddr52 = <0x3>;
H A Dsprd,sdhci-r11.yaml53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":
107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
H A Dmmc-controller-common.yaml348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi153 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
/linux/drivers/mmc/core/
H A Ddebugfs.c148 str = "mmc DDR52"; in mmc_ios_show()
/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c192 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi450 ti,otap-del-sel-ddr52 = <0x5>;
454 ti,itap-del-sel-ddr52 = <0x0>;