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Searched full:ddr0 (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd9571mwv.yaml42 - bit 0: DDR0
/linux/drivers/clk/
H A Dclk-eyeq.c400 { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg64 = 0x04C },
673 { .index = 0, .name = "pll-ddr0", .reg64 = 0x074 },
712 { .compatible = "mobileye,eyeq6h-ddr0-olb", .data = &eqc_eyeq6h_ddr0_match_data },
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun8i-a33.c96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
394 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
459 "pll-ddr0", "pll-ddr1" };
H A Dccu-sun50i-a64.c97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
519 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
593 "pll-ddr0", "pll-ddr1" };
H A Dccu-sun50i-h6.c58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
267 "pll-ddr0", "pll-periph0-4x" };
373 static const char * const dram_parents[] = { "pll-ddr0" };
H A Dccu-sun50i-h616.c60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
288 "pll-ddr0", "pll-ddr1" };
384 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
H A Dccu-sun50i-a100.c66 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
304 static const char * const mbus_parents[] = { "dcxo24M", "pll-ddr0",
H A Dccu-sun20i-d1.c59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
H A Dccu-sun55i-a523.c54 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
/linux/drivers/pmdomain/actions/
H A Dowl-sps.c264 .name = "DDR0",
/linux/arch/powerpc/boot/
H A D4xx.c124 /* DDR0 registers */
/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c704 "ddr0", CGU_CLK_GATE,