Searched full:cmu_hsi0 (Results 1 – 7 of 7) sorted by relevance
94 - description: CMU_HSI0 BUS clock (from CMU_TOP)95 - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)96 - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)97 - description: CMU_HSI0 DPGTC clock (from CMU_TOP)147 cmu_hsi0: clock-controller@10a00000 {
73 clocks = <&cmu_hsi0 7>,74 <&cmu_hsi0 5>,75 <&cmu_hsi0 8>;
95 &cmu_hsi0 {
1374 cmu_hsi0: clock-controller@16000000 { label
216 /* CMU_HSI0 */
316 /* CMU_HSI0 */
1185 /* ---- CMU_HSI0 ------------------------------------------------------------ */1187 /* Register Offset definitions for CMU_HSI0 (0x10a00000) */1238 /* Parent clock list for CMU_HSI0 muxes */