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/linux/drivers/pwm/
H A Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
11 #include <linux/clk.h>
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
29 struct clk *clk[]; member
39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
40 u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2); in jz4740_pwm_can_use_chn()
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H A Dpwm-sunplus.c1 // SPDX-License-Identifier: GPL-2.0
3 * PWM device driver for SUNPLUS SP7021 SoC
7 * https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
9 * Reference Manual(PWM module):
10 * https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM
13 * - Only supports normal polarity.
14 * - It output low when PWM channel disabled.
15 * - When the parameters change, current running period will not be completed
17 * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
23 #include <linux/clk.h>
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H A Dpwm-spear.c12 #include <linux/clk.h>
21 #include <linux/pwm.h>
27 /* PWM registers and bits definitions */
47 * struct spear_pwm_chip - struct representing pwm chip
49 * @mmio_base: base address of pwm chip
50 * @clk: pointer to clk structure of pwm chip
54 struct clk *clk; member
65 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
72 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
75 static int spear_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in spear_pwm_config() argument
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H A Dpwm-vt8500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-vt8500.c
16 #include <linux/pwm.h>
18 #include <linux/clk.h>
28 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) argument
29 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) argument
30 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) argument
31 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) argument
49 struct clk *clk; member
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) in vt8500_pwm_busy_wait()
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H A Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM Controller Driver for HiSilicon BVT SoCs
9 #include <linux/clk.h>
15 #include <linux/pwm.h>
36 struct clk *clk; member
82 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_enable() argument
86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
90 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_disable() argument
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
98 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_config() argument
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H A Dpwm-clk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Clock based PWM controller
7 * This is an "adapter" driver that allows PWM consumers to use
8 * system clocks with duty cycle control as PWM outputs.
11 * - Due to the fact that exact behavior depends on the underlying
13 * - Underlying clock may not be able to give 0% or 100% duty cycle
15 * - When the PWM is disabled, the clock will be disabled as well,
17 * - The clk API doesn't expose the necessary calls to implement
27 #include <linux/clk.h>
28 #include <linux/pwm.h>
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H A Dpwm-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM framework driver for Cirrus Logic EP93xx
9 * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
12 * platform device ep93xx-pwm.0 - PWMOUT
15 * platform device ep93xx-pwm.0 - PWMOUT
16 * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
23 #include <linux/clk.h>
26 #include <linux/pwm.h>
37 struct clk *clk; member
45 static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in ep93xx_pwm_apply() argument
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H A Dpwm-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-pxa.c
5 * simple driver for PWM (Pulse Width Modulator) controller
7 * 2008-02-13 initial version
10 * Links to reference manuals for some of the supported PWM chips can be found
14 * - When PWM is stopped, the current PWM period stops abruptly at the next
24 #include <linux/clk.h>
26 #include <linux/pwm.h>
35 /* PWM has_secondary_pwm? */
36 { "pxa25x-pwm", 0 },
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H A Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
7 * PWM output inversion: According to the SiFive Reference manual
12 * hard-tied to 0 (XNOR), which effectively inverts the comparison so that
21 * **active-high** PWM interface.
25 * - When changing both duty cycle and period, we cannot prevent in
28 * - The hardware cannot generate a 0% duty cycle.
29 * - The hardware generates only inverted output.
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H A Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
9 #include <linux/clk.h>
17 #include <linux/pwm.h>
35 struct clk *clk; member
36 struct clk *pclk;
62 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
66 u64 prescaled_ns = (u64)pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
67 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
73 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
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H A Dpwm-keembay.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Keem Bay PWM driver
10 * - Upon disabling a channel, the currently running
17 #include <linux/clk.h>
22 #include <linux/pwm.h>
34 /* PWM Register offset */
40 struct clk *clk; member
54 static int keembay_clk_enable(struct device *dev, struct clk *clk) in keembay_clk_enable() argument
58 ret = clk_prepare_enable(clk); in keembay_clk_enable()
62 return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk); in keembay_clk_enable()
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H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
13 #include <linux/clk.h>
21 #include <linux/pwm.h>
46 #define PWM_PRD(prd) (((prd) - 1) << 16)
83 struct clk *bus_clk;
84 struct clk *clk; member
98 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
104 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
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H A Dpwm-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk.h>
13 #include <linux/pwm.h>
18 * The Kona PWM has some unusual characteristics. Here are the main points.
34 * 5) When the external clock that feeds the PWM is disabled, output is pegged
60 struct clk *clk; member
74 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
78 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
82 * it. Failing to do this may result in no PWM signal. in kona_pwmc_prepare_for_settings()
89 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
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H A Dpwm-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk.h>
13 #include <linux/pwm.h>
40 struct clk *clk; member
49 static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in mxs_pwm_apply() argument
60 * If the PWM channel is disabled, make sure to turn on the in mxs_pwm_apply()
64 if (!pwm_is_enabled(pwm)) { in mxs_pwm_apply()
65 ret = clk_prepare_enable(mxs->clk); in mxs_pwm_apply()
70 if (!state->enabled && pwm_is_enabled(pwm)) in mxs_pwm_apply()
71 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); in mxs_pwm_apply()
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H A Dpwm-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
14 #include <linux/pwm.h>
18 struct clk *clk; member
30 static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in lpc32xx_pwm_config() argument
37 c = clk_get_rate(lpc32xx->clk); in lpc32xx_pwm_config()
43 return -ERANGE; in lpc32xx_pwm_config()
48 duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256, in lpc32xx_pwm_config()
55 val = readl(lpc32xx->base); in lpc32xx_pwm_config()
58 writel(val, lpc32xx->base); in lpc32xx_pwm_config()
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H A Dpwm-rz-mtu3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L MTU3a PWM Timer driver
8 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…
11 * - When PWM is disabled, the output is driven to Hi-Z.
12 * - While the hardware supports both polarities, the driver (for now)
14 * - HW uses one counter and two match components to configure duty_cycle
16 * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM
18 * - MTU{1, 2} channels have a single IO, whereas all other HW channels have
20 * - Each IO is modelled as an independent PWM channel.
21 * - rz_mtu3_channel_io_map table is used to map the PWM channel to the
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H A Dpwm-sophgo-sg2042.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PWM Controller Driver
9 * - After reset, the output of the PWM channel is always high.
11 * - When HLPERIOD or PERIOD is reconfigured, PWM will start to
14 * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will
16 * - SG2044 supports both polarities, SG2042 only normal polarity.
18 * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM
21 #include <linux/clk.h>
27 #include <linux/pwm.h>
52 * struct sg2042_pwm_ddata - private driver data
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H A Dpwm-atmel-tcb.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
21 #include <linux/pwm.h>
36 unsigned div; /* PWM clock divider */
37 unsigned duty; /* PWM duty expressed in clk cycles */
38 unsigned period; /* PWM period expressed in clk cycles */
54 struct clk *clk; member
55 struct clk *gclk;
56 struct clk *slow_clk;
69 struct pwm_device *pwm) in atmel_tcb_pwm_request() argument
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H A Dpwm-meson.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * PWM controller driver for Amlogic Meson SoCs.
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
32 #include <linux/clk.h>
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H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
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H A Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
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H A Dpwm-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
12 #include <linux/pwm.h>
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
28 struct clk *clk; member
37 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_request() argument
42 value = readl(pc->base + PWM_CONTROL); in bcm2835_pwm_request()
43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 writel(value, pc->base + PWM_CONTROL); in bcm2835_pwm_request()
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H A Dpwm-clps711x.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cirrus Logic CLPS711X PWM driver
7 #include <linux/clk.h>
12 #include <linux/pwm.h>
16 struct clk *clk; member
24 static int clps711x_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in clps711x_pwm_request() argument
27 unsigned int freq = clk_get_rate(priv->clk); in clps711x_pwm_request()
30 return -EINVAL; in clps711x_pwm_request()
33 pwm->args.period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq); in clps711x_pwm_request()
38 static int clps711x_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in clps711x_pwm_apply() argument
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H A Dpwm-intel-lgm.c1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
17 #include <linux/clk.h>
21 #include <linux/pwm.h>
36 #define LGM_PWM_MAX_RPM (BIT(16) - 1)
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
23 clocks = <&clk LOONGSON2_NODE_CLK>;
27 ref_100m: clock-ref-100m {
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