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/linux/Documentation/devicetree/bindings/gpio/
H A Dxlnx,gpio-xilinx.yaml52 description: This option sets this GPIO channel1 bits in input mode.
60 description: This option sets this GPIO channel1 bits in output mode.
69 channel1.
80 description: The value defines the bit width of the GPIO channel1.
110 of each bit of GPIO channel1.
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml24 have to be different. Channel0 outputs odd pixels and channel1 outputs
30 data. In split mode, channel0 outputs odd pixels and channel1 outputs even
/linux/Documentation/devicetree/bindings/net/can/
H A Drenesas,rcar-canfd.yaml106 - channel1
212 channel1 {
/linux/drivers/mfd/
H A Dmxs-lradc.c58 DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH1_IRQ, "mxs-lradc-channel1"),
77 DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH1_IRQ, "mxs-lradc-channel1"),
/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-common.dtsi36 channel1 {
H A Dr8a779a0-falcon.dts53 channel1 {
H A Drz-smarc-common.dtsi90 channel1 {
H A Dr8a779h0-gray-hawk-single.dts198 channel1 {
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml37 Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
/linux/drivers/edac/
H A Dpnd2_edac.c672 bool channel1; in sys2pmi() local
676 channel1 = mot_hit ? ((bool)((addr >> mot_intlv_bit) & 1)) : in sys2pmi()
678 *pmiidx |= (u32)channel1; in sys2pmi()
704 bool channel1; in sys2pmi() local
711 channel1 = (addr >> mot_intlv_bit) & 1; in sys2pmi()
714 channel1 = hash_by_mask(contig_addr, chan_hash_mask); in sys2pmi()
717 *pmiidx |= (u32)channel1; in sys2pmi()
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml125 lpddr-channel1 {
/linux/tools/virtio/virtio-trace/
H A DREADME65 id=channel1,name=trace-path-cpu0\
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8qm-ldb.c239 "failed to power on channel1 PHY: %d\n", in imx8qm_ldb_bridge_atomic_enable()
274 "failed to power off channel1 PHY: %d\n", in imx8qm_ldb_bridge_atomic_disable()
H A Dimx8qxp-ldb.c509 * transmits odd pixels and channel1 transmits even pixels. in imx8qxp_ldb_parse_dt_companion()
/linux/sound/soc/codecs/
H A Dadau1373.c669 SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
761 SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
862 { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
908 DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
H A Dda7218.c745 SOC_SINGLE("AGS Channel1 Switch", DA7218_AGS_ENABLE,
783 SOC_DOUBLE_EXT("ALC Channel1 Switch", DA7218_ALC_CTRL1,
805 SOC_DOUBLE_EXT("Mic Level Detect Channel1 Switch", DA7218_LVL_DET_CTRL,
/linux/arch/arm/mach-spear/
H A Dtime.c33 #define CLKSRC 1 /* gpt0, channel1 as clocksource */
/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h271 /* inline function to enable/disable channel1 */
302 /* inline function to enable interrupt for channel1 */
H A Dvpif.c261 /* Channel1 */
/linux/Documentation/iio/
H A Diio_devbuf.rst127 - channel1: index: 1, type: be:u32/32>>0
/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi333 channel1 {
353 channel1 {
/linux/include/sound/
H A Dak4117.h77 #define AK4117_CS12 (1<<5) /* channel status select, 0 = channel1, 1 = channel2 */
/linux/drivers/gpu/drm/kmb/
H A Dkmb_dsi.c529 * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 in mipi_tx_fg_cfg_regs()
635 * REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 in mipi_tx_multichannel_fifo_cfg()
/linux/drivers/gpu/drm/msm/registers/display/
H A Dmdp4.xml464 <bitfield name="CHANNEL1" pos="7" type="boolean"/>
/linux/drivers/input/misc/
H A Dati_remote2.c97 …PARM_DESC(channel_mask, "Bitmask of channels to accept <15:Channel16>...<1:Channel2><0:Channel1>");

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