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/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
55 #define TAS5086_CLOCK_RATIO(val) (val << 2)
56 #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
67 #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
[all …]
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
24 2: SD/MMC controller 1 (unused)
25 3: SD/MMC controller 2 (unused)
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 #define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
55 # define SSI_MODE_FRAME 2
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
[all …]
H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 - $ref: input.yaml#
16 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
17 additional Hall-effect and inductive sensing capabilities.
24 - azoteq,iqs269a
25 - azoteq,iqs269a-00
26 - azoteq,iqs269a-d0
[all …]
/linux/sound/pci/emu10k1/
H A Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
43 * 2 = Capture output 2.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
47 * 2 = Capture output 2.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
51 * 2 = Capture output 2.
[all …]
/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
34 * playback periods_min=2, periods_max=8
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dti,tlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
[all …]
H A Dst,sta32x.txt7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
31 #define CHNL_CTRL_SRC_INPUT_MASK GENMASK(2, 0)
33 /* Channel Image Control Register */
91 #define CHNL_IMG_CTRL_DEINT_WEAVE_ODD_EVEN 2
106 #define CHNL_IMG_CTRL_CSC_MODE_MASK GENMASK(2, 1)
109 #define CHNL_IMG_CTRL_CSC_MODE_RGB2YUV 2
113 /* Channel Output Buffer Control Register */
121 #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_50 2
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
43 #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
69 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
113 #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
158 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
159 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
[all …]
/linux/drivers/char/xillybus/
H A Dxillybus_core.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/dma-mapping.h>
53 #define XILLYMSG_OPCODE_QUIESCEACK 2
75 * register_mutex is endpoint-specific, and is held when non-atomic
87 * wr_mutex -> rd_mutex -> register_mutex -> wr_spinlock -> rd_spinlock
101 dev_warn(endpoint->dev, in malformed_message()
102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
108 * which is the natural case MSI and several other hardware-oriented
120 struct xilly_channel *channel; in xillybus_isr() local
122 buf = ep->msgbuf_addr; in xillybus_isr()
[all …]
/linux/include/linux/dma/
H A Dsprd-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
16 * we can request 2 dma channels, one for source channel, and another one for
17 * destination channel. Each channel is independent, and has its own
18 * configurations. Once the source channel's transaction is done, it will
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
28 * @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
29 * support the 2-stage transfer.
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5770r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandru Tachici <alexandru.tachici@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD5770R.pdf
21 - adi,ad5770r
26 avdd-supply:
31 iovdd-supply:
35 vref-supply:
41 adi,external-resistor:
[all …]
/linux/drivers/hwmon/peci/
H A Ddimmtemp.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2021 Intel Corporation
7 #include <linux/devm-helpers.h>
12 #include <linux/peci-cpu.h>
20 /* Max number of channel ranks and DIMM index per channel */
25 #define CHAN_RANK_MAX_ON_BDXD 2
26 #define DIMM_IDX_MAX_ON_BDXD 2
28 #define DIMM_IDX_MAX_ON_SKX 2
30 #define DIMM_IDX_MAX_ON_ICX 2
32 #define DIMM_IDX_MAX_ON_ICXD 2
[all …]
/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* MIDI 1.0 Channel Control (7bit) */
31 UMP_CC_BREATH = 2,
134 u32 channel:4; member
140 u32 channel:4;
153 u32 channel:4; member
159 u32 channel:4;
172 u32 channel:4; member
178 u32 channel:4;
191 u32 channel:4; member
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,pm8018-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
29 xoadc-ref-supply:
[all …]
/linux/drivers/hwmon/
H A Dnct7904.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
59 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
60 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
61 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
62 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
69 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
71 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */
84 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */
85 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */
[all …]
/linux/sound/usb/caiaq/
H A Dcontrol.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 struct snd_usb_caiaqdev *cdev = caiaqdev(chip->card); in control_info()
25 int pos = kcontrol->private_value; in control_info()
29 uinfo->count = 1; in control_info()
32 switch (cdev->chip.usb_id) { in control_info()
37 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
38 uinfo->value.integer.min = 0; in control_info()
39 uinfo->value.integer.max = 2; in control_info()
54 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
55 uinfo->value.integer.min = 0; in control_info()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Delo3-dma-0.dtsi20 * Foundation, either version 2 of that License or (at your option) any
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 interrupts = <28 2 0 0>;
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
50 interrupts = <29 2 0 0>;
[all …]
H A Delo3-dma-1.dtsi20 * Foundation, either version 2 of that License or (at your option) any
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 interrupts = <32 2 0 0>;
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
50 interrupts = <33 2 0 0>;
[all …]
H A Delo3-dma-2.dtsi20 * Foundation, either version 2 of that License or (at your option) any
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
45 interrupts = <464 2 0 0>;
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
50 interrupts = <465 2 0 0>;
[all …]

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