Lines Matching +full:channel +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
16 * we can request 2 dma channels, one for source channel, and another one for
17 * destination channel. Each channel is independent, and has its own
18 * configurations. Once the source channel's transaction is done, it will
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
28 * @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
29 * support the 2-stage transfer.
30 * @SPRD_DMA_SRC_CHN0: Channel used as source channel 0.
31 * @SPRD_DMA_SRC_CHN1: Channel used as source channel 1.
32 * @SPRD_DMA_DST_CHN0: Channel used as destination channel 0.
33 * @SPRD_DMA_DST_CHN1: Channel used as destination channel 1.
35 * Now the DMA controller can supports 2 groups 2-stage transfer.
46 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
49 * @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
50 * automatically once the source channel's fragment request is done.
51 * @SPRD_DMA_BLOCK_DONE_TRG: Trigger the transaction of destination channel
52 * automatically once the source channel's block request is done.
53 * @SPRD_DMA_TRANS_DONE_TRG: Trigger the transaction of destination channel
54 * automatically once the source channel's transfer request is done.
55 * @SPRD_DMA_LIST_DONE_TRG: Trigger the transaction of destination channel
56 * automatically once the source channel's link-list request is done.
71 * @SPRD_DMA_LIST_REQ: link-list request mode
75 * contain several fragments. Link-list mode means we can save several DMA
100 * @SPRD_DMA_LIST_INT: link-list done interrupt when one link-list request
118 * struct sprd_dma_linklist - DMA link-list address structure
119 * @virt_addr: link-list virtual address to configure link-list node
120 * @phy_addr: link-list physical address to link DMA transfer
121 * @wrap_addr: the wrap address for link-list mode, which means once the
125 * The Spreadtrum DMA controller supports the link-list mode, that means slaves
129 * link-list register.
131 * Just as shown below, the link-list pointer register will be pointed to the
132 * physical address of 'configuration 1', and the 'configuration 1' link-list
133 * pointer will be pointed to 'configuration 2', and so on.
136 * done, DMA controller will load 'configuration 2' automatically, until all
139 * Note: The last link-list pointer should point to the physical address
144 * ====================== -----------------------
145 *| | | configuration 1 |<---
146 *| DMA controller | ------->| | |
150 *| linklist pointer reg |---- ----| linklist pointer | |
151 * ====================== | ----------------------- |
153 * | ----------------------- |
154 * | | configuration 2 | |
155 * --->| | |
159 * ----| linklist pointer | |
160 * | ----------------------- |
162 * | ----------------------- |
164 * --->| | |
171 * | ----------------------- |
173 * --->| | |
177 * | linklist pointer |----
178 * -----------------------
180 * To support the link-list mode, DMA slaves should allocate one segment memory
181 * from always-on IRAM or dma coherent memory to store these groups of DMA