Home
last modified time | relevance | path

Searched full:cacheability (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5.yaml118 cacheability attributes but is connected to a non-coherent
169 cacheability attributes but is connected to a non-coherent
/linux/arch/x86/include/asm/
H A Dagp.h12 * mappings with different cacheability attributes for the same
/linux/drivers/iommu/
H A Dmsm_iommu.h16 /* Cacheability attributes of MSM IOMMU mappings */
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml211 The standard Ssccptr extension for main memory (cacheability and
475 The standard Ziccamoa extension for main memory (cacheability and
482 The standard Ziccif extension for main memory (cacheability and
489 The standard Zicclsm extension for main memory (cacheability and
/linux/arch/sparc/include/asm/
H A Dswift.h21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S41 li r3,0x1200 /* enable i-fetch cacheability */
/linux/include/linux/
H A Dio-pgtable.h84 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h172 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_meta.h277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
/linux/drivers/irqchip/
H A Dirq-gic-v3-its.c3203 * remove the cacheability attributes as in its_cpu_init_lpis()
3229 * cacheability attributes as well. in its_cpu_init_lpis()
5308 * remove the cacheability attributes as in its_probe_one()
/linux/include/uapi/drm/
H A Di915_drm.h134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
/linux/tools/include/uapi/drm/
H A Di915_drm.h134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
/linux/arch/arm64/kvm/
H A Dmmu.c313 * we then fully enforce cacheability of RAM, no matter what the guest
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c2075 * Program cacheability overrides to not allocate cache in a6xx_llc_activate()
/linux/arch/sparc/mm/
H A Dinit_64.c2327 * set on M7 processor. Compute the value of cacheability in paging_init()
/linux/arch/m68k/kernel/
H A Dhead.S215 * the cacheability of the kernel bits.
/linux/Documentation/
H A Dmemory-barriers.txt2989 Chapter 5: Memory Accesses and Cacheability
/linux/Documentation/translations/sp_SP/
H A Dmemory-barriers.txt3107 Capítulo 5: Memory Accesses and Cacheability