1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21965aae3SH. Peter Anvin #ifndef _ASM_X86_AGP_H 31965aae3SH. Peter Anvin #define _ASM_X86_AGP_H 4bb898558SAl Viro 5ca5999fdSMike Rapoport #include <linux/pgtable.h> 6bb898558SAl Viro #include <asm/cacheflush.h> 7bb898558SAl Viro 8bb898558SAl Viro /* 9bb898558SAl Viro * Functions to keep the agpgart mappings coherent with the MMU. The 10bb898558SAl Viro * GART gives the CPU a physical alias of pages in memory. The alias 11bb898558SAl Viro * region is mapped uncacheable. Make sure there are no conflicting 12*163b0991SIngo Molnar * mappings with different cacheability attributes for the same 13bb898558SAl Viro * page. This avoids data corruption on some CPUs. 14bb898558SAl Viro */ 15bb898558SAl Viro 16bb898558SAl Viro #define map_page_into_agp(page) set_pages_uc(page, 1) 17bb898558SAl Viro #define unmap_page_from_agp(page) set_pages_wb(page, 1) 18bb898558SAl Viro 19bb898558SAl Viro /* 20bb898558SAl Viro * Could use CLFLUSH here if the cpu supports it. But then it would 21bb898558SAl Viro * need to be called for each cacheline of the whole page so it may 22bb898558SAl Viro * not be worth it. Would need a page for it. 23bb898558SAl Viro */ 24bb898558SAl Viro #define flush_agp_cache() wbinvd() 25bb898558SAl Viro 261965aae3SH. Peter Anvin #endif /* _ASM_X86_AGP_H */ 27