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Searched +full:blit +full:- +full:engine (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx8qxp-dc-blit-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Blit Engine
10 A blit operation (block based image transfer) reads up to 3 source images
35 Modify colors by linear or non-linear transformations.
47 Performs a re-sampling of the source image with any pattern. The sample
59 - Liu Ying <victor.liu@nxp.com>
63 const: fsl,imx8qxp-dc-blit-engine
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H A Dfsl,imx8qxp-dc-pixel-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Pixel Engine
13 functions. Interconnection of Processing Units is re-configurable.
16 - Liu Ying <victor.liu@nxp.com>
20 const: fsl,imx8qxp-dc-pixel-engine
28 "#address-cells":
31 "#size-cells":
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H A Dfsl,imx8qxp-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 components that include a blit engine for 2D graphics accelerations, display
17 +---------------------------+------------+------------------+-+-+------+
20 | @@@@@@@@@@@ +----------+------------+------------+ | | | |
22 X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
24 | @@@@@@@@@@@ | | Pixel Engine | | | | |
27 A | *********** | | | | | | | Blit | |
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,imx8qxp-dc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
19 Alternatively the un-masked trigger signals for all HW events are provided,
26 - Liu Ying <victor.liu@nxp.com>
30 const: fsl,imx8qxp-dc-intc
38 interrupt-controller: true
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dstericsson,db8500-prcmu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit
10 - Linus Walleij <linus.walleij@linaro.org>
13 The DB8500 Power Reset and Control Management Unit is an XP70 8-bit
14 microprocessor that is embedded in the always-on power domain of the
20 pattern: '^prcmu@[0-9a-f]+$'
23 description: The device is compatible both to the device-specific
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