Lines Matching +full:blit +full:- +full:engine
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 components that include a blit engine for 2D graphics accelerations, display
17 +---------------------------+------------+------------------+-+-+------+
20 | @@@@@@@@@@@ +----------+------------+------------+ | | | |
22 X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
24 | @@@@@@@@@@@ | | Pixel Engine | | | | |
27 A | *********** | | | | | | | Blit | |
28 H <-+->| Configure | | V V V V | | Engine | |
31 | | | Engine | | Engine | | | | |
35 R <-+--| Control | | | Display | | | |
37 | @@@@@@@@@@@ +------------------------------------+ | |
39 +--------------------------+----------------+-------+---------+--------+
47 - Liu Ying <victor.liu@nxp.com>
51 const: fsl,imx8qxp-dc
62 reset-names:
64 - const: axi
65 - const: cfg
67 power-domains:
70 "#address-cells":
73 "#size-cells":
79 "^command-sequencer@[0-9a-f]+$":
85 const: fsl,imx8qxp-dc-command-sequencer
87 "^display-engine@[0-9a-f]+$":
93 const: fsl,imx8qxp-dc-display-engine
95 "^interrupt-controller@[0-9a-f]+$":
101 const: fsl,imx8qxp-dc-intc
103 "^pixel-engine@[0-9a-f]+$":
109 const: fsl,imx8qxp-dc-pixel-engine
111 "^pmu@[0-9a-f]+$":
117 const: fsl,imx8qxp-dc-axi-performance-counter
120 - compatible
121 - reg
122 - clocks
123 - power-domains
124 - "#address-cells"
125 - "#size-cells"
126 - ranges
131 - |
132 #include <dt-bindings/clock/imx8-lpcg.h>
133 #include <dt-bindings/firmware/imx/rsrc.h>
135 display-controller@56180000 {
136 compatible = "fsl,imx8qxp-dc";
139 power-domains = <&pd IMX_SC_R_DC_0>;
140 #address-cells = <1>;
141 #size-cells = <1>;
144 interrupt-controller@56180040 {
145 compatible = "fsl,imx8qxp-dc-intc";
148 interrupt-controller;
149 interrupt-parent = <&dc0_irqsteer>;
150 #interrupt-cells = <1>;
164 interrupt-names = "store9_shdload",
215 pixel-engine@56180800 {
216 compatible = "fsl,imx8qxp-dc-pixel-engine";
219 #address-cells = <1>;
220 #size-cells = <1>;
224 display-engine@5618b400 {
225 compatible = "fsl,imx8qxp-dc-display-engine";
227 reg-names = "top", "cfg";
228 interrupt-parent = <&dc0_intc>;
230 interrupt-names = "shdload", "framecomplete", "seqcomplete";
231 power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
232 #address-cells = <1>;
233 #size-cells = <1>;