Lines Matching +full:blit +full:- +full:engine
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Pixel Engine
13 functions. Interconnection of Processing Units is re-configurable.
16 - Liu Ying <victor.liu@nxp.com>
20 const: fsl,imx8qxp-dc-pixel-engine
28 "#address-cells":
31 "#size-cells":
37 "^blit-engine@[0-9a-f]+$":
43 const: fsl,imx8qxp-dc-blit-engine
45 "^constframe@[0-9a-f]+$":
51 const: fsl,imx8qxp-dc-constframe
53 "^extdst@[0-9a-f]+$":
59 const: fsl,imx8qxp-dc-extdst
61 "^fetchdecode@[0-9a-f]+$":
67 const: fsl,imx8qxp-dc-fetchdecode
69 "^fetcheco@[0-9a-f]+$":
75 const: fsl,imx8qxp-dc-fetcheco
77 "^fetchlayer@[0-9a-f]+$":
83 const: fsl,imx8qxp-dc-fetchlayer
85 "^fetchwarp@[0-9a-f]+$":
91 const: fsl,imx8qxp-dc-fetchwarp
93 "^hscaler@[0-9a-f]+$":
99 const: fsl,imx8qxp-dc-hscaler
101 "^layerblend@[0-9a-f]+$":
107 const: fsl,imx8qxp-dc-layerblend
109 "^matrix@[0-9a-f]+$":
115 const: fsl,imx8qxp-dc-matrix
117 "^safety@[0-9a-f]+$":
123 const: fsl,imx8qxp-dc-safety
125 "^vscaler@[0-9a-f]+$":
131 const: fsl,imx8qxp-dc-vscaler
134 - compatible
135 - reg
136 - clocks
137 - "#address-cells"
138 - "#size-cells"
139 - ranges
144 - |
145 #include <dt-bindings/clock/imx8-lpcg.h>
147 pixel-engine@56180800 {
148 compatible = "fsl,imx8qxp-dc-pixel-engine";
151 #address-cells = <1>;
152 #size-cells = <1>;
156 compatible = "fsl,imx8qxp-dc-constframe";
158 reg-names = "pec", "cfg";
162 compatible = "fsl,imx8qxp-dc-extdst";
164 reg-names = "pec", "cfg";
165 interrupt-parent = <&dc0_intc>;
167 interrupt-names = "shdload", "framecomplete", "seqcomplete";
171 compatible = "fsl,imx8qxp-dc-constframe";
173 reg-names = "pec", "cfg";
177 compatible = "fsl,imx8qxp-dc-extdst";
179 reg-names = "pec", "cfg";
180 interrupt-parent = <&dc0_intc>;
182 interrupt-names = "shdload", "framecomplete", "seqcomplete";
186 compatible = "fsl,imx8qxp-dc-constframe";
188 reg-names = "pec", "cfg";
192 compatible = "fsl,imx8qxp-dc-extdst";
194 reg-names = "pec", "cfg";
195 interrupt-parent = <&dc0_intc>;
197 interrupt-names = "shdload", "framecomplete", "seqcomplete";
201 compatible = "fsl,imx8qxp-dc-constframe";
203 reg-names = "pec", "cfg";
207 compatible = "fsl,imx8qxp-dc-extdst";
209 reg-names = "pec", "cfg";
210 interrupt-parent = <&dc0_intc>;
212 interrupt-names = "shdload", "framecomplete", "seqcomplete";
216 compatible = "fsl,imx8qxp-dc-fetchwarp";
218 reg-names = "pec", "cfg";
222 compatible = "fsl,imx8qxp-dc-fetchlayer";
224 reg-names = "pec", "cfg";
228 compatible = "fsl,imx8qxp-dc-layerblend";
230 reg-names = "pec", "cfg";
234 compatible = "fsl,imx8qxp-dc-layerblend";
236 reg-names = "pec", "cfg";
240 compatible = "fsl,imx8qxp-dc-layerblend";
242 reg-names = "pec", "cfg";
246 compatible = "fsl,imx8qxp-dc-layerblend";
248 reg-names = "pec", "cfg";