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/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Duart-routing.yaml17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
24 which owns the system configuration policy, to configure how UARTs and
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dirq-chip-model.rst27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h156 /* UARTs */
233 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
235 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
236 /* UARTs are driven by internal divided clock */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
/linux/drivers/tty/serial/
H A DKconfig136 This enables the driver for the on-chip UARTs of the Atmel
169 Say Y here if you wish to have the internal AT91 UARTs
172 64). This is necessary if you also want other UARTs, such as
173 external 8250/16C550 compatible UARTs.
187 This enables the driver for the on-chip UARTs of the Amlogic
207 This enables the driver for the on-chip UARTs of the Cirrus
225 Support for the on-chip UARTs on the Samsung
261 Support for the on-chip UARTs on the NVIDIA Tegra series SOCs
692 Those are UARTs completely different from the Standard UARTs on the
766 UARTs.
[all …]
/linux/drivers/tty/serial/8250/
H A DKconfig183 This enables support for FPGA based UARTs found on many MEN
185 and 16z125 UARTs.
389 erratum for Freescale 16550 UARTs in the 8250 driver. It also
397 driver for the Altera 16550 UART. One or more Altera 16550 UARTs
502 its UARTs, say Y to this option. If unsure, say N.
540 I/O UARTs that are not covered by the more generic SERIAL_8250_PCI
H A D8250_pxa.c3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
169 MODULE_DESCRIPTION("driver for PXA on-board UARTS");
H A D8250_exar.c423 * Exar UARTs have a SLEEP register that enables or disables each UART in exar_pm()
432 * XR17V35x UARTs have an extra fractional divisor register (DLD)
511 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled in default_setup()
597 * Some Exar UARTs have an auto-tristate feature while others require setting
1401 * These Exar UARTs have an extra interrupt indicator that could fire for a
1704 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
/linux/include/uapi/linux/
H A Dserial_core.h27 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
143 /* Altera UARTs */
H A Dserial_reg.h98 some Freescale UARTs) */
239 * The Intel XScale on-chip UARTs define these bits
348 * Extra serial register definitions for the internal UARTs
/linux/arch/parisc/include/asm/
H A Dserial.h6 * This is used for 16550-compatible UARTs
/linux/drivers/char/mwave/
H A DMakefile12 # To have the mwave driver disable other uarts if necessary
/linux/arch/mips/include/asm/mach-rc32434/
H A Dirq.h17 /* 16550 UARTs */
/linux/include/linux/ssb/
H A Dssb_driver_extif.h11 * support external devices such as UARTs and the BCM2019 Bluetooth
13 * The external interface core also contains 2 on-chip 16550 UARTs, clock
H A Dssb_driver_chipcommon.h8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
29 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
/linux/arch/arm/mach-s3c/
H A Ddev-uart-s3c64xx.c25 /* 64xx uarts are closer together */
H A Dpm-common.c43 * restore the UARTs state yet
/linux/Documentation/devicetree/bindings/serial/
H A D8250_omap.yaml7 title: 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs
H A Dqcom,msm-uartdm.yaml20 Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
H A Dserial.yaml14 This document lists a set of generic properties for describing UARTs in a
/linux/drivers/tty/serial/jsm/
H A Djsm_driver.c131 * 2 I/O Mapped UARTs and Status in jsm_probe_one()
133 * 4 Memory Mapped UARTs and Status in jsm_probe_one()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dstarfive,jh7110-sys-pinctrl.yaml16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
/linux/Documentation/driver-api/serial/
H A Dserial-iso7816.rst14 Some CPUs/UARTs (e.g., Microchip AT91) contain a built-in mode capable of
/linux/arch/sparc/include/asm/
H A Dns87303.h57 /* Tape UARTs and Parallel Port Config Register (TUP) bits */
/linux/arch/mips/alchemy/common/
H A Dplatform.c131 printk(KERN_INFO "Alchemy: missing support for UARTs\n"); in alchemy_setup_uarts()
136 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); in alchemy_setup_uarts()
/linux/arch/arm/mach-lpc32xx/
H A Dserial.c106 /* Setup UART clock modes for all UARTs, disable autoclock */ in lpc32xx_serial_init()

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