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/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DStage.h1 //===---------------------- Stage.h -----------------------------*- C++ -*-===//
10 /// This file defines a stage.
27 class Stage {
28 Stage *NextInSequence = nullptr;
31 Stage(const Stage &Other) = delete;
32 Stage &operator=(const Stage &Other) = delete;
38 Stage() = default;
39 virtual ~Stage();
44 /// Returns true if some instructions are still executing this stage.
57 /// The primary action that this stage performs on instruction IR.
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H A DExecuteStage.h10 /// This file defines the execution stage of a default instruction pipeline.
23 #include "llvm/MCA/Stages/Stage.h"
28 class ExecuteStage final : public Stage {
34 // True if this stage should notify listeners of HWPressureEvents.
43 // Used to notify instructions eliminated at register renaming stage.
55 // This stage works under the assumption that the Pipeline will eventually
56 // execute a retire stage. We don't need to check if pipelines and/or
70 // moved to the next stage (i.e. RetireStage).
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h27 /// discrete time slots needed to complete the stage. Units represent
29 /// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many
30 /// cycles should elapse from the start of this stage to the start of
31 /// the next stage in the itinerary. A value of -1 indicates that the
32 /// next stage should start immediately after the current one.
36 /// indicates that the stage occupies FU x for 1 cycle and that
37 /// the next stage starts immediately after this one.
40 /// indicates that the stage occupies either FU x or FU y for 2
41 /// consecutive cycles and that the next stage starts one cycle
42 /// after this stage start
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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json39 …on is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded",
42 …ion is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded"
45 …iting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded",
48 …aiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded"
51 …ock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded",
54 …lock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded"
57 …backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load",
60 … backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load"
63 …ckend, store. This event counts every cycle where there is a stall in the Wr stage due to a store",
66 …ackend, store. This event counts every cycle where there is a stall in the Wr stage due to a store"
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/freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json126 "PublicDescription": "Level 1 stage 2 TLB refill",
129 "BriefDescription": "L1 stage 2 TLB refill"
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
141 "BriefDescription": "Page walk, L1 stage-1 hit"
144 "PublicDescription": "Page walk cache level-2 stage-1 hit",
147 "BriefDescription": "Page walk, L2 stage-1 hit"
150 "PublicDescription": "Page walk cache level-1 stage-2 hit",
153 "BriefDescription": "Page walk, L1 stage-2 hit"
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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json39 … is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaitin…
42 … is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaitin…
45 …to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load",
48 … to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load"
51 … the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store",
54 …o the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store"
57 …load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
60 …load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
63 …, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
66 …, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note
28 // The Stage of an instruction defines the mapping between logical loop
38 // in stage 0 and I1 in stage 1:
41 // [stage 0] x = I0
42 // [stage 1] I1 x (from stage 0)
79 /// maintain a Cycle and Stage.
93 /// The stage for each instruction.
94 DenseMap<MachineInstr *, int> Stage; variable
96 /// The number of stages in this schedule (Max(Stage) + 1).
106 /// \arg Stage Stage index for all instructions in ScheduleInstrs.
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/freebsd/crypto/krb5/src/lib/kadm5/srv/
H A Dkadm5_hook.c133 if (stage == KADM5_HOOK_STAGE_PRECOMMIT) \
143 int stage, krb5_principal princ, krb5_boolean keepold, in k5_kadm5_hook_chpass() argument
148 stage, princ, keepold, in k5_kadm5_hook_chpass()
155 int stage, kadm5_principal_ent_t princ, long mask, in k5_kadm5_hook_create() argument
160 stage, princ, mask, n_ks_tuple, ks_tuple, newpass)); in k5_kadm5_hook_create()
166 int stage, kadm5_principal_ent_t princ, long mask) in k5_kadm5_hook_modify() argument
168 ITERATE(modify, (context, h->data, stage, princ, mask)); in k5_kadm5_hook_modify()
174 int stage, krb5_principal oprinc, krb5_principal nprinc) in k5_kadm5_hook_rename() argument
176 ITERATE(rename, (context, h->data, stage, oprinc, nprinc)); in k5_kadm5_hook_rename()
182 int stage, krb5_principal princ) in k5_kadm5_hook_remove() argument
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/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp154 Stage = IS_INVALID; in reset()
164 assert(Stage == IS_INVALID); in dispatch()
165 Stage = IS_DISPATCHED; in dispatch()
174 assert(Stage == IS_READY); in execute()
175 Stage = IS_EXECUTING; in execute()
177 // Set the cycles left before the write-back stage. in execute()
183 // Transition to the "executed" stage if this is a zero-latency instruction. in execute()
185 Stage = IS_EXECUTED; in execute()
189 assert(Stage == IS_READY && "Invalid internal state!"); in forceExecuted()
191 Stage = IS_EXECUTED; in forceExecuted()
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H A DPipeline.cpp32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
56 const std::unique_ptr<Stage> &S = *I; in runCycle()
67 Stage &FirstStage = *Stages[0]; in runCycle()
77 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
86 void Pipeline::appendStage(std::unique_ptr<Stage> S) { in appendStage()
87 assert(S && "Invalid null stage in input!"); in appendStage()
89 Stage *Last = Stages.back().get(); in appendStage()
/freebsd/crypto/krb5/src/plugins/kadm5_hook/test/
H A Dmain.c42 int stage, in log_call() argument
49 printf("%s: stage %s principal %s\n", in log_call()
51 (stage == KADM5_HOOK_STAGE_PRECOMMIT) ? "precommit" : "postcommit", in log_call()
60 int stage, in chpass() argument
66 log_call(context, "chpass", stage, princ); in chpass()
74 int stage, in create() argument
80 log_call(context, "create", stage, princ->principal); in create()
85 rename_hook(krb5_context context, kadm5_hook_modinfo *modinfo, int stage, in rename_hook() argument
88 log_call(context, "rename", stage, oprinc); in rename_hook()
/freebsd/crypto/krb5/src/include/krb5/
H A Dkadm5_hook_plugin.h34 * precommit stage that runs before the operation is committed to the
82 /** In this stage, any plugin failure prevents following plugins from
85 /** In this stage, plugin failures are logged but otherwise ignored.*/
111 * @param stage is an integer from #kadm5_hook_stage enumeration
117 int stage,
126 int stage,
135 int stage,
141 int stage, krb5_principal);
148 int stage, krb5_principal, krb5_principal);
153 int stage, krb5_principal alias,
/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DStage.cpp1 //===---------------------- Stage.cpp ---------------------------*- C++ -*-===//
10 /// This file defines a stage.
15 #include "llvm/MCA/Stages/Stage.h"
21 Stage::~Stage() = default;
23 void Stage::addListener(HWEventListener *Listener) { in addListener()
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DFunctionComparator.h122 /// On this stage method, in case when lossless bitcast is not possible
125 /// Stage 0: If types are equal in terms of cmpTypes, then we can go straight
129 /// Stage 1: Types that satisfies isFirstClassType conditions are always
131 /// Stage 2: Vector is greater then non-vector.
137 /// Stage 3: Pointer types are greater than non-pointers. If both types are
141 /// Stage 4: Types are neither vectors, nor pointers. And they differ.
154 /// It ignores types on this stage and only compares bits from L and R.
227 /// Stage 0: Value that is function itself is always greater then others.
230 /// Stage 1: Constants are greater than non-constants.
233 /// Stage
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/freebsd/share/man/man8/
H A Dnanobsd.865 Skip the disk image build stage.
69 stage of the build.
73 stage of the build.
75 Do not cleanup before each build stage.
78 stage and adds -DNO_CLEAN to the make command line
79 used for each build stage (world and kernel).
87 stage of the build.
91 stage of the build.
254 stage of the build.
258 stage of the build.
H A Ddiskless.850 The stage-1 bootstrap, typically PXE built into your Ethernet
51 card, loads a second-stage boot program.
53 The second-stage boot program, typically
65 First, the stage-1 bootstrap loads the stage-2 boot program over
67 The stage-1 bootstrap typically uses
83 The stage-2 boot program then loads additional modules and the kernel.
94 the second stage boot files and kernel.
95 The stage-2 program uses
123 client, the stage-2 boot will load your server's kernel as the kernel for
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h363 #define BWN_NPHY_TXF_20CO_AS0 BWN_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
364 #define BWN_NPHY_TXF_20CO_AS1 BWN_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
365 #define BWN_NPHY_TXF_20CO_AS2 BWN_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
366 #define BWN_NPHY_TXF_20CO_B32S0 BWN_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
367 #define BWN_NPHY_TXF_20CO_B1S0 BWN_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
368 #define BWN_NPHY_TXF_20CO_B32S1 BWN_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
369 #define BWN_NPHY_TXF_20CO_B1S1 BWN_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
370 #define BWN_NPHY_TXF_20CO_B32S2 BWN_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
371 #define BWN_NPHY_TXF_20CO_B1S2 BWN_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
387 #define BWN_NPHY_TXF_40CO_AS0 BWN_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A Dpipeline.json27 …he LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty",
30 …the LS IQs are full with micro-operations waiting for issuing, and the dispatch stage is not empty"
33 …d DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty",
36 …nd DP1 IQs are full with micro-operations waiting for issuing, and the despatch stage is not empty"
39 …nstruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_inst…
42 …nstruction, excluding No Operations (NOPs), that cannot move to the issue stage because accpt_inst…
/freebsd/lib/libc/posix1e/
H A Dacl_support.c175 int stage = ACL_USER_OBJ; in _posix1e_acl_check() local
194 if (stage > ACL_USER_OBJ) in _posix1e_acl_check()
196 stage = ACL_USER; in _posix1e_acl_check()
202 if (stage > ACL_USER) in _posix1e_acl_check()
204 stage = ACL_USER; in _posix1e_acl_check()
214 if (stage > ACL_GROUP_OBJ) in _posix1e_acl_check()
216 stage = ACL_GROUP; in _posix1e_acl_check()
222 if (stage > ACL_GROUP) in _posix1e_acl_check()
224 stage = ACL_GROUP; in _posix1e_acl_check()
233 if (stage > ACL_MASK) in _posix1e_acl_check()
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/freebsd/crypto/krb5/src/plugins/preauth/spake/
H A Dspake_kdc.c49 * stage (16-bit unsigned integer)
57 * The only currently supported version is 1. stage is 0 if the cookie was
58 * sent with a challenge message. stage is n>0 if the cookie was sent with an
61 * stage-0 cookie, represented in the scalar marshalling form of the group; for
64 * hash after updating with the support and challenge messages for a stage-0
65 * cookie, or the final hash for other cookies. For a stage 0 cookie, there
89 int version, stage; in parse_cookie() local
100 stage = k5_input_get_uint16_be(&in); in parse_cookie()
111 *stage_out = stage; in parse_cookie()
129 make_cookie(int stage, int32_t group, const krb5_data *spake, in make_cookie() argument
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/freebsd/contrib/bmake/unit-tests/
H A Dvarname-makeflags.mk13 .if !make(*stage*)
70 # At this stage, MAKEFLAGS is not yet involved.
81 # At this point, the stage 1 make provides the environment variable
87 # The 'DOLLARS=\$\{varname\}' assignment is escaped so that the stage
160 @${MAKE} -f ${MAKEFILE} STAGE=1 VAR=value override_stage_1
164 # variable, in this case provided by stage 0.
179 @${MAKE} -f ${MAKEFILE} STAGE=2 override_stage_2
182 @echo '$@: STAGE=<${STAGE}> VAR=<${VAR}>'
/freebsd/contrib/sendmail/libmilter/docs/
H A Dsmfi_setsymlist.html16 int stage,
21 for a protocol stage.
51 <TR><TD>stage</TD>
52 <TD>the protocol stage during which the macro list should be used.
82 <LI><CODE>stage</CODE> is not a valid protocol stage,
84 <CODE>stage</CODE> has been set before.
/freebsd/usr.bin/clang/clang/
H A Dclang.153 This stage handles tokenization of the input source file, macro expansion,
55 output of this stage is typically called a \(dq.i\(dq (for C), \(dq.ii\(dq (for C++),
59 This stage parses the input file, translating preprocessor tokens into a
62 the code is well formed. This stage is responsible for generating most of
63 the compiler warnings as well as parse errors. The output of this stage is
67 This stage translates an AST into low\-level intermediate code (known as
70 The output of this stage is typically called a \(dq.s\(dq file or \(dqassembly\(dq file.
77 This stage runs the target assembler to translate the output of the
78 compiler into a target object file. The output of this stage is typically
82 This stage runs the target linker to merge multiple object files into an
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/freebsd/sbin/reboot/
H A Dboot_i386.860 A three-stage bootstrap is employed.
62 third-stage bootstrap program,
64 This third stage provides more sophisticated control over the booting
224 This option only affects second-stage bootstrap,
269 first stage bootstrap file
271 second stage bootstrap file
273 third stage bootstrap
280 When disk-related errors occur, these are reported by the second-stage
316 is reported by the second-stage bootstrap, it generally means that this
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DModuloSchedule.cpp31 OS << "[stage " << getStage(MI) << " @" << getCycle(MI) << "c] " << *MI; in print()
78 // stage difference for each use. Keep the maximum value. in expand()
116 // the iteration, or stage, that the instruction is scheduled in. This is in generatePipelinedLoop()
118 // in each stage of the pipelined loop. in generatePipelinedLoop()
202 // Generate a basic block for each stage, not including the last stage, in generateProlog()
216 // Generate instructions for each appropriate stage. Process instructions in generateProlog()
253 /// block for each stage that needs to complete.
277 // Generate a basic block for each stage, not including the last stage, in generateEpilog()
373 // Compute the stage number for the initial value of the Phi, which in generateExistingPhis()
417 // Phis cannot exceed the number of prolog stages. Each stage can in generateExistingPhis()
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