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/linux/fs/nls/
H A DKconfig44 native language character sets. These character sets are stored
56 native language character sets. These character sets are stored
68 native language character sets. These character sets are stored
81 native language character sets. These character sets are stored in
97 native language character sets. These character sets are stored in
112 native language character sets. These character sets are stored in
123 native language character sets. These character sets are stored in
134 native language character sets. These character sets are stored in
145 native language character sets. These character sets are stored in
156 native language character sets. These character sets are stored in
[all …]
/linux/Documentation/ABI/stable/
H A Dconfigfs-nvmet13 addr_adrfam: Shows or sets the address family. Accepted
16 addr_portid: Shows or sets the port identifier (u16).
18 addr_traddr: Shows or sets the transport address string.
20 addr_trsvcid: Shows or sets the transport service identifier.
22 addr_trtype: Shows or sets the transport type. Accepted
26 addr_treq: Shows or sets the transport security requirements.
48 attribute shows or sets whether this referral is enabled
56 Shows or sets the inline data size for this port. Default
65 Shows or sets the ANA (Asymmetric Namespace Access) state
75 Shows or sets whether protection information (PI) is
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/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi51 i-cache-sets = <256>;
54 d-cache-sets = <256>;
67 i-cache-sets = <256>;
70 d-cache-sets = <256>;
82 i-cache-sets = <256>;
85 d-cache-sets = <256>;
97 i-cache-sets = <256>;
100 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4.dtsi65 i-cache-sets = <256>;
68 d-cache-sets = <256>;
79 i-cache-sets = <256>;
82 d-cache-sets = <256>;
93 i-cache-sets = <256>;
96 d-cache-sets = <256>;
107 i-cache-sets = <256>;
110 d-cache-sets = <256>;
121 i-cache-sets = <256>;
124 d-cache-sets = <256>;
[all …]
H A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
99 cache-sets = <512>;
109 cache-sets = <512>;
H A Dk3-am625.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
H A Dk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
/linux/arch/mips/mm/
H A Dc-octeon.c183 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
191 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
193 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
203 c->icache.sets = 8; in probe_octeon()
206 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
210 c->dcache.sets = 8; in probe_octeon()
211 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
217 c->icache.sets = 16; in probe_octeon()
[all …]
H A Dsc-mips.c153 unsigned long sets, line_sz, assoc; in mips_sc_probe_cm3() local
158 sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE; in mips_sc_probe_cm3()
159 sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE); in mips_sc_probe_cm3()
160 if (sets) in mips_sc_probe_cm3()
161 c->scache.sets = 64 << sets; in mips_sc_probe_cm3()
171 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe_cm3()
214 c->scache.sets = 64 << tmp; in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
241 c->scache.sets = 256; in mips_sc_probe()
247 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe()
/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-fm-tx.rst31 Sets the RDS Programme Identification field for transmission.
34 Sets the RDS Programme Type field for transmission. This encodes up
38 Sets the Programme Service name (PS_NAME) for transmission. It is
50 Sets the Radio Text info for transmission. It is a textual
65 Sets the Mono/Stereo bit of the Decoder Identification code. If set,
69 Sets the
75 Sets the Compressed bit of the Decoder Identification code. If set,
79 Sets the Dynamic PTY bit of the Decoder Identification code. If set,
107 Sets the audio deviation limiter feature release time. Unit is in
121 Sets the gain for audio compression feature. It is a dB value. The
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap806-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
H A Darmada-ap807-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi29 i-cache-sets = <128>;
46 d-cache-sets = <64>;
48 d-tlb-sets = <1>;
52 i-cache-sets = <64>;
54 i-tlb-sets = <1>;
73 d-cache-sets = <64>;
75 d-tlb-sets = <1>;
79 i-cache-sets = <64>;
81 i-tlb-sets = <1>;
100 d-cache-sets = <64>;
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H A Dfu740-c000.dtsi29 i-cache-sets = <128>;
47 d-cache-sets = <64>;
49 d-tlb-sets = <1>;
53 i-cache-sets = <128>;
55 i-tlb-sets = <1>;
74 d-cache-sets = <64>;
76 d-tlb-sets = <1>;
80 i-cache-sets = <128>;
82 i-tlb-sets = <1>;
101 d-cache-sets = <64>;
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi43 /* Source for d/i-cache-line-size and d/i-cache-sets
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
107 /* Source for cache-line-size + cache-sets
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H A Dbcm2837.dtsi42 /* Source for d/i-cache-line-size and d/i-cache-sets
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
109 /* Source for cache-line-size + cache-sets
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h41 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
104 /* Sets the DAC A sense value to high */
106 /* Sets the DAC B sense value to high */
108 /* Sets the DAC C sense value to high */
112 /* Sets the slew rate. Must be preserved in software */
340 /* Sets the subcarrier DDA to reset frequency every other field */
342 /* Sets the subcarrier DDA to reset frequency every fourth field */
344 /* Sets the subcarrier DDA to reset frequency every eighth field */
346 /* Sets the subcarrier DDA to never reset the frequency */
348 /* Sets the peak amplitude of the colorburst.*/
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-r1.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
146 i-cache-sets = <256>;
149 d-cache-sets = <128>;
163 i-cache-sets = <256>;
166 d-cache-sets = <128>;
[all …]
H A Djuno.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
169 d-cache-sets = <128>;
[all …]
H A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
170 d-cache-sets = <128>;
[all …]
H A Dfvp-base-revc.dts78 i-cache-sets = <256>;
81 d-cache-sets = <256>;
92 i-cache-sets = <256>;
95 d-cache-sets = <256>;
106 i-cache-sets = <256>;
109 d-cache-sets = <256>;
120 i-cache-sets = <256>;
123 d-cache-sets = <256>;
134 i-cache-sets = <256>;
137 d-cache-sets = <256>;
[all …]
H A Dmorello.dtsi40 i-cache-sets = <512>;
43 d-cache-sets = <512>;
53 cache-sets = <2048>;
67 i-cache-sets = <512>;
70 d-cache-sets = <512>;
80 cache-sets = <2048>;
94 i-cache-sets = <512>;
97 d-cache-sets = <512>;
107 cache-sets = <2048>;
121 i-cache-sets = <512>;
[all …]
/linux/include/media/i2c/
H A Dtc358743.h37 * Sets DDC5V_MODE in register DDC_CTL.
75 * Sets HDMI_DET_V in register HDMI_DET.
81 * Sets PHY_AUTO_RST2 in register PHY_CTL2.
87 * Sets PHY_AUTO_RST3 in register PHY_CTL2.
93 * Sets PHY_AUTO_RST4 in register PHY_CTL2.
99 * Sets H_PI_RST in register HV_RST.
105 * Sets V_PI_RST in register HV_RST.
/linux/arch/openrisc/kernel/
H A Dcacheinfo.c23 this_leaf->number_of_sets = cache->sets; in ci_leaf_init()
46 cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); in init_cache_level()
49 cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size; in init_cache_level()
54 cpuinfo->dcache.sets, cpuinfo->dcache.ways); in init_cache_level()
61 cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); in init_cache_level()
64 cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size; in init_cache_level()
69 cpuinfo->icache.sets, cpuinfo->icache.ways); in init_cache_level()
/linux/include/uapi/linux/
H A Dultrasound.h32 * _GUS_NUMVOICES - Sets max. number of concurrent voices (P1=14-31, default 16)
38 * _GUS_VOICEBALA - Sets voice balance (P1, 0=left, 7=middle and 15=right, default 7)
39 * _GUS_VOICEFREQ - Sets voice (sample) playback frequency (P1=Hz)
40 * _GUS_VOICEVOL - Sets voice volume (P1=volume, 0xfff=max, 0xeff=half, 0x000=off)
41 * _GUS_VOICEVOL2 - Sets voice volume (P1=volume, 0xfff=max, 0xeff=half, 0x000=off)
45 * _GUS_RAMPRANGE - Sets limits for volume ramping (P1=low volume, P2=high volume)
46 * _GUS_RAMPRATE - Sets the speed for volume ramping (P1=scale, P2=rate)
47 * _GUS_RAMPMODE - Sets the volume ramping mode (P1=ramping mode)

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