Home
last modified time | relevance | path

Searched full:spe (Results 1 – 25 of 104) sorted by relevance

12345

/linux/tools/perf/util/
H A Darm-spe.c3 * Arm Statistical Profiling Extensions (SPE) support
33 #include "arm-spe.h"
34 #include "arm-spe-decoder/arm-spe-decoder.h"
35 #include "arm-spe-decoder/arm-spe-pkt-decoder.h"
106 struct arm_spe *spe; member
137 static void arm_spe_dump(struct arm_spe *spe __maybe_unused, in arm_spe_dump()
147 ". ... ARM SPE data: size %#zx bytes\n", in arm_spe_dump()
176 static void arm_spe_dump_event(struct arm_spe *spe, unsigned char *buf, in arm_spe_dump_event() argument
180 arm_spe_dump(spe, buf, len); in arm_spe_dump_event()
190 queue = &speq->spe->queues.queue_array[speq->queue_nr]; in arm_spe_get_trace()
[all …]
/linux/tools/perf/Documentation/
H A Dperf-arm-spe.txt1 perf-arm-spe(1)
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
16 The SPE (Statistical Profiling Extension) feature provides accurate attribution of latencies and
32 This is chosen from a sample population, for SPE this is an IMPLEMENTATION DEFINED choice of all
34 architecture provides a mechanism for the SPE driver to infer the minimum interval at which it should
64 Up until this point no decoding of the SPE data was done by either the kernel or Perf. Only when the
67 recording. These samples are the same as if normal sampling was done by Perf without using SPE,
69 just the instruction pointer, but an SPE sample can have data addresses and latency attributes.
84 However, SPE does not provide any call-graph information, and relies on statistical methods.
123 The SPE interrup
[all...]
H A Dperf-c2c.txt25 limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to
27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
28 statistical nature of Arm SPE sampling, not every memory operation will be
194 …| Arm | Default | -e spe-ldst | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store…
195 …| SPE |---------------+-----------------+------------------------------------------------------…
196 …| | Load only | -e spe-load | arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_l…
198 …| | Store only | -e spe-store | arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/ …
383 linkperf:perf-record[1], linkperf:perf-mem[1], linkperf:perf-arm-spe[1]
H A Dperf-mem.txt26 On Arm64 this uses SPE to sample load and store operations, therefore hardware
27 and kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide.
28 Due to the statistical nature of SPE sampling, not every memory operation will
211 linkperf:perf-record[1], linkperf:perf-report[1], linkperf:perf-arm-spe[1]
/linux/tools/perf/tests/shell/
H A Dtest_arm_spe.sh2 # Check Arm SPE trace data recording and synthesized samples (exclusive)
4 # Uses the 'perf record' to record trace data of Arm SPE events;
5 # then verify if any SPE event samples are generated by SPE with
46 # from arm-spe.c/arm_spe_synth_events()
88 arm_spe_report "SPE snapshot testing" $err
96 arm_spe_report "SPE system-wide testing" 2
107 arm_spe_report "SPE system-wide testing" $err
111 echo "SPE discard mode"
121 arm_spe_report "SPE discard mode not present" 2
125 # Test can use wildcard SPE instance and Perf will only open the event
[all …]
H A Dtest_arm_spe_fork.sh2 # Check Arm SPE doesn't hang when there are forks
44 echo "SPE hang test: FAIL"
47 echo "SPE hang test: PASS"
/linux/arch/powerpc/boot/dts/
H A Dicon.dts33 model = "PowerPC,440SPe";
53 compatible = "ibm,uic-440spe","ibm,uic";
63 compatible = "ibm,uic-440spe","ibm,uic";
75 compatible = "ibm,uic-440spe","ibm,uic";
87 compatible = "ibm,uic-440spe","ibm,uic";
99 compatible = "ibm,sdr-440spe";
104 compatible = "ibm,cpr-440spe";
109 compatible = "ibm,mq-440spe";
114 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
131 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
[all …]
H A Dkatmai.dts37 model = "PowerPC,440SPe";
57 compatible = "ibm,uic-440spe","ibm,uic";
67 compatible = "ibm,uic-440spe","ibm,uic";
79 compatible = "ibm,uic-440spe","ibm,uic";
91 compatible = "ibm,uic-440spe","ibm,uic";
103 compatible = "ibm,sdr-440spe";
108 compatible = "ibm,cpr-440spe";
113 compatible = "ibm,mq-440spe";
118 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
135 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
[all …]
/linux/Documentation/devicetree/bindings/perf/
H A Dspe-pmu.yaml4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
37 spe-pmu {
/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dppc440spe-adma.txt15 - compatible : "ibm,i2o-440spe";
22 compatible = "ibm,i2o-440spe";
32 - compatible : "ibm,dma-440spe";
45 compatible = "ibm,dma-440spe";
82 - compatible : "ibm,mq-440spe";
88 compatible = "ibm,mq-440spe";
/linux/lib/crypto/powerpc/
H A Dsha256.h3 * SHA-256 Secure Hash Algorithm, SPE optimized
6 * about the SPE registers so it can run from interrupt context.
31 /* We just start SPE operations and will save SPE registers later. */ in spe_begin()
H A Dsha1.h29 /* We just start SPE operations and will save SPE registers later. */ in spe_begin()
/linux/arch/powerpc/platforms/ps3/
H A Dspu.c28 * enum spe_type - Type of spe to create.
29 * @spe_type_logical: Standard logical spe.
40 * struct spe_shadow - logical spe shadow register area.
42 * Read-only shadow of spe registers.
66 * enum spe_ex_state - Logical spe execution state.
71 * The execution state (status) of the logical spe as reported in
83 * @masks[]: Array of cached spe interrupt masks, indexed by class.
96 * @spe_id: HV spe id returned by lv1_construct_logical_spe().
97 * @resource_id: HV spe resource id returned by
99 * @priv2_addr: lpar address of spe priv2 area returned by
[all …]
/linux/arch/powerpc/include/asm/
H A Ddcr-regs.h28 /* CPRs (440GX and 440SP/440SPe) */
32 /* SDRs (440GX and 440SP/440SPe) */
162 * DCR register offsets for 440SP/440SPe I2O/DMA controller.
169 /* 440SP/440SPe Software Reset DCR */
173 /* 440SP/440SPe Memory Queue DCR offsets */
/linux/tools/perf/arch/arm64/util/
H A Dmem-events.c9 E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,min_latency=%u/", NULL, true, 0),
10 E("spe-store", "%s/ts_enable=1,pa_enable=1,store_filter=1/", NULL, false, 0),
11 …E("spe-ldst", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", NULL, tru…
H A Darm-spe.c3 * Arm Statistical Profiling Extensions (SPE) support
28 #include "../../../util/arm-spe.h"
117 /* Find the associate Arm SPE PMU for the CPU */ in arm_spe_save_cpu_header()
122 /* No Arm SPE PMU is found */ in arm_spe_save_cpu_header()
281 * Set this only so that perf report knows that SPE generates memory info. It has no effect in arm_spe_setup_evsel()
282 * on the opening of the event or the SPE data produced. in arm_spe_setup_evsel()
288 * inform that the resulting output's SPE samples contain physical addresses in arm_spe_setup_evsel()
351 pr_err("Invalid mmap size for ARM SPE: must be at least %zuKiB and a power of 2\n", in arm_spe_setup_aux_buffer()
416 pr_err("Arm SPE: Frequency is not supported. " in arm_spe_recording_options()
/linux/arch/powerpc/kernel/
H A Dhead_85xx.S587 /* Define SPE handlers for e500v2 */
589 /* SPE Unavailable */
602 /* SPE Floating Point Data */
611 /* SPE Floating Point Round */
774 /* Note that the SPE support is closely modeled after the AltiVec
779 * Disable SPE for the task which had SPE previously,
780 * and save its SPE registers in its thread_struct.
781 * Enables SPE for use in the kernel on return.
782 * On SMP we know the SPE units are free, since we give it up every
787 mtmsr r5 /* enable use of SPE now */
[all …]
H A Dcpu_specs_44x.h187 { /* 440SPe Rev. A */
190 .cpu_name = "440SPe Rev. A",
200 { /* 440SPe Rev. B */
203 .cpu_name = "440SPe Rev. B",
H A Dsignal_32.c244 * We only save the altivec/spe registers if the process has used
245 * altivec/spe instructions at some point.
316 /* save spe registers */ in __unsafe_save_user_regs()
353 * We only save the altivec/spe registers if the process has used
354 * altivec/spe instructions at some point.
540 * Force the process to reload the spe registers from in restore_user_regs()
541 * current->thread when it next does spe instructions. in restore_user_regs()
544 BUILD_BUG_ON(sizeof(current->thread.spe) != ELF_NEVRREG * sizeof(u32)); in restore_user_regs()
547 /* restore spe registers from the stack */ in restore_user_regs()
548 unsafe_copy_from_user(&current->thread.spe, &sr->mc_vregs, in restore_user_regs()
[all …]
/linux/arch/powerpc/platforms/
H A DKconfig.cputype393 config SPE config
394 bool "SPE Support"
399 Extensions (SPE) to the PowerPC processor. The kernel currently
400 supports saving and restoring SPE registers, and turning on the
401 'spe enable' bit so user processes can execute SPE instructions.
404 SPE (e500, otherwise known as 85xx series), but does not have any
405 effect on a non-spe cpu (it does, however add code to the kernel).
/linux/sound/soc/sdca/
H A Dsdca_functions.c345 case SDCA_CTL_TYPE_S(SPE, PRIVATE): in find_sdca_control_label()
347 case SDCA_CTL_TYPE_S(SPE, PRIVACY_POLICY): in find_sdca_control_label()
349 case SDCA_CTL_TYPE_S(SPE, PRIVACY_LOCKSTATE): in find_sdca_control_label()
351 case SDCA_CTL_TYPE_S(SPE, PRIVACY_OWNER): in find_sdca_control_label()
353 case SDCA_CTL_TYPE_S(SPE, AUTHTX_CURRENTOWNER): in find_sdca_control_label()
355 case SDCA_CTL_TYPE_S(SPE, AUTHTX_MESSAGEOFFSET): in find_sdca_control_label()
357 case SDCA_CTL_TYPE_S(SPE, AUTHTX_MESSAGELENGTH): in find_sdca_control_label()
359 case SDCA_CTL_TYPE_S(SPE, AUTHRX_CURRENTOWNER): in find_sdca_control_label()
361 case SDCA_CTL_TYPE_S(SPE, AUTHRX_MESSAGEOFFSET): in find_sdca_control_label()
363 case SDCA_CTL_TYPE_S(SPE, AUTHRX_MESSAGELENGTH): in find_sdca_control_label()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A De500v2_power_isa.dtsi47 power-isa-sp.fd; // SPE.Embedded Float Scalar Double
48 power-isa-sp.fs; // SPE.Embedded Float Scalar Single
49 power-isa-sp.fv; // SPE.Embedded Float Vector
/linux/tools/perf/util/arm-spe-decoder/
H A DBuild1 perf-util-y += arm-spe-pkt-decoder.o arm-spe-decoder.o
/linux/drivers/dma/ppc4xx/
H A Ddma.h3 * 440SPe's DMA engines support header file
119 * DMAx hardware registers (p.515 in 440SPe UM 1.22)
153 * I2O hardware registers (p.528 in 440SPe UM 1.22)
/linux/arch/powerpc/platforms/44x/
H A DKconfig71 select 440SPe
218 select 440SPe
273 config 440SPe

12345