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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVProcessors.td91 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
104 // to change to the appropriate rv32/rv64 version.
127 def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
458 def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
479 def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
504 def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
H A DRISCVRegisterInfo.td75 let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
79 let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
216 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
223 def XLenPairFVT : ValueTypeByHwMode<[RV32],
226 [RV32, RV64],
322 [RV32, RV64],
H A DRISCVMergeBaseOffset.cpp234 // RV32 ignores the upper 32 bits. ADDIW sign extends the result. in foldLargeOffset()
497 // RV32 ignores the upper 32 bits. in foldIntoMemoryOps()
H A DRISCVSubtarget.cpp81 CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; in initializeSubtargetDependencies()
H A DRISCVExpandPseudoInsts.cpp329 // sequence for RV32.
378 // RV32.
H A DRISCVFeatures.td1649 // Feature32Bit exists to mark CPUs that support RV32 to distinguish them from
1652 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
1662 defvar RV32 = DefaultMode;
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVISAInfo.cpp487 if (Arch.consume_front("rv32")) in parseNormalizedArchString()
562 // ISA string must begin with rv32, rv64, or a profile. in parseArchString()
564 if (Arch.consume_front("rv32")) { in parseArchString()
602 "string must begin with rv32{i,e,g}, rv64{i,e,g}, or a supported " in parseArchString()
781 return getError("'zcf' is only supported for 'rv32'"); in checkDependency()
785 return getError("'xwchc' is only supported for 'rv32'"); in checkDependency()
796 return getError("'zclsd' is only supported for 'rv32'"); in checkDependency()
803 return getError("'zilsd' is only supported for 'rv32'"); in checkDependency()
807 return getError("'" + Twine(Ext) + "'" + " is only supported for 'rv32'"); in checkDependency()
879 // Add Zcf if C and F are enabled on RV32. in updateImplication()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp327 // Use FPR64 for s64 loads on rv32. in getInstrMapping()
361 // Use FPR64 for s64 stores on rv32. in getInstrMapping()
392 // Use FPR64 for s64 select on rv32. in getInstrMapping()
467 // Use FPR64 for s64 merge on rv32. in getInstrMapping()
478 // Use FPR64 for s64 unmerge on rv32. in getInstrMapping()
H A DRISCVLegalizerInfo.cpp504 // FIXME: Support s128 for rv32 when libcall handling is able to use sret. in RISCVLegalizerInfo()
577 .libcallFor(ST.is64Bit(), {{s32, s128}, {s64, s128}}) // FIXME RV32. in RISCVLegalizerInfo()
599 .libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}}) // FIXME RV32. in RISCVLegalizerInfo()
646 // Handle case of s64 element vectors on RV32. If the subtarget does not have in RISCVLegalizerInfo()
1021 // Handle case of s64 element vectors on rv32 in legalizeSplatVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp142 reportError("RV32 target requires an RV32 CPU"); in validate()
145 reportError("RV32 and RV64 can't be combined"); in validate()
H A DRISCVMatInt.cpp101 // RV32 without being a pessimization. in generateInstSeqImpl()
284 // will always be true for RV32 and will often be true for RV64. in generateInstSeq()
289 "Expected RV32 to only need 2 instructions"); in generateInstSeq()
H A DRISCVMCTargetDesc.cpp82 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; in createRISCVMCSubtargetInfo()
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_riscv.cpp130 // J 44 bytes (rv32) in patchSled()
145 // We typecast the Tracing Hook to a 32 bit value for RV32 in patchSled()
155 // case of RV64 and store words for RV32. Subsequently, we have LUI - and in in patchSled()
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DRISCV.cpp215 // rv32g | rv32*d -> ilp32d in getRISCVABI()
217 // rv32* -> ilp32 in getRISCVABI()
366 return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32"; in getRISCVTargetCPU()
/freebsd/sys/conf/
H A DMakefile.riscv32 # Note: For rv32 the start address is different (0x80400000).
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h293 constexpr uint8_t RV32 = 1; variable
305 uint8_t inst_type = RV32 | RV64 | RV128;
H A DEmulateInstructionRISCV.cpp540 {"FLW", 0xE003, 0x6000, DecodeC_FLW, RV32},
541 {"FSW", 0xE003, 0xE000, DecodeC_FSW, RV32},
542 {"FLWSP", 0xE003, 0x6002, DecodeC_FLWSP, RV32},
543 {"FSWSP", 0xE003, 0xE002, DecodeC_FSWSP, RV32},
545 {"FLDSP", 0xE003, 0x2002, DecodeC_FLDSP, RV32 | RV64},
546 {"FSDSP", 0xE003, 0xA002, DecodeC_FSDSP, RV32 | RV64},
547 {"FLD", 0xE003, 0x2000, DecodeC_FLD, RV32 | RV64},
548 {"FSD", 0xE003, 0xA000, DecodeC_FSD, RV32 | RV64},
648 inst_type = RV32; in Decode()
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/riscv/
H A Dsave.S13 // The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
H A Drestore.S18 // 4s for rv32 since this is the minimum grouping which will maintain the
/freebsd/crypto/openssl/crypto/aes/asm/
H A Daes-riscv32-zkn.pl123 # Encoding for aes32dsi rd, rs1, rs2, bs instruction on RV32
135 # Encoding for aes32dsmi rd, rs1, rs2, bs instruction on RV32
147 # Encoding for aes32esi rd, rs1, rs2, bs instruction on RV32
159 # Encoding for aes32esmi rd, rs1, rs2, bs instruction on RV32
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp804 {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
806 {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
850 {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml522 load/store pair for RV32 with the main manual") of riscv-isa-manual.
527 Load/Store Pair for RV32. As with Zilsd, this extension was ratified
528 in commit f88abf1 ("Integrating load/store pair for RV32 with the
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp853 // If this a RV32 and the immediate is a uimm32, sign extend it to 32 bits.
1035 OS << ' ' << (Imm.IsRV64 ? "rv64" : "rv32") << '>'; in print()
1345 // There are some GPRF64AsFPR instructions that have no RV32 equivalent. We in validateTargetOperandClass()
1346 // reject them at parsing thinking we should match as GPRPairAsFPR for RV32. in validateTargetOperandClass()
1347 // So we explicitly accept them here for RV32 to allow the generic code to in validateTargetOperandClass()
1973 ErrorMsg += "is RV32 only"; in parseCSRSystemRegister()
2523 // If this is an RV64 GPRPair instruction, there is no RV32 version so we can in parseGPRPair()
3009 return Error(Loc, "bad arch string switching from rv64 to rv32"); in resetToArch()
3011 return Error(Loc, "bad arch string switching from rv32 to rv64"); in resetToArch()
3870 // On RV32 the immediate here can either be a signed or an unsigned in processInstruction()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DRISCV.cpp149 // list and pass indirectly on RV32. in computeInfo()
157 // This is a normal scalar > 2*XLen, such as fp128 on RV32. in computeInfo()
/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m4242 # There are 2 architectures (with variants): rv32* and rv64*.

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