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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, th
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H A Dsifive,plic-1.0.0.txt1 SiFive Platform-Level Interrupt Controller (PLIC)
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
6 specification. The PLIC connects all external interrupts in the system to all
18 with priority below this threshold will not cause the PLIC to raise its
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
37 - interrupts-extended : Specifies which contexts are connected to the PLIC,
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H A Driscv,cpu-intc.txt16 via the platform-level interrupt controller (PLIC).
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmicrochip-mpfs.dtsi163 interrupt-parent = <&plic>;
177 plic: interrupt-controller@c000000 { label
178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
203 interrupt-parent = <&plic>;
215 interrupt-parent = <&plic>;
227 interrupt-parent = <&plic>;
239 interrupt-parent = <&plic>;
251 interrupt-parent = <&plic>;
262 interrupt-parent = <&plic>;
274 interrupt-parent = <&plic>;
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H A Dmpfs.dtsi217 interrupt-parent = <&plic>;
231 plic: interrupt-controller@c000000 {
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
248 interrupt-parent = <&plic>;
299 interrupt-parent = <&plic>;
311 interrupt-parent = <&plic>;
323 interrupt-parent = <&plic>;
335 interrupt-parent = <&plic>;
347 interrupt-parent = <&plic>;
209 plic: interrupt-controller@c000000 { global() label
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H A Dmpfs-icicle-kit-fabric.dtsi23 interrupt-parent = <&plic>;
38 interrupt-parent = <&plic>;
H A Dmicrochip-mpfs-fabric.dtsi20 interrupt-parent = <&plic>;
H A Dmpfs-m100pfs-fabric.dtsi26 interrupt-parent = <&plic>;
H A Dmpfs-polarberry-fabric.dtsi26 interrupt-parent = <&plic>;
/freebsd/sys/riscv/riscv/
H A Dplic.c107 { "sifive,plic-1.0.0", 1 },
108 { "thead,c900-plic", 1 },
245 * From sifive,plic-1.0.0.yaml: in plic_map_intr()
247 * "The PLIC supports both edge-triggered and level-triggered in plic_map_intr()
248 * interrupts. For edge-triggered interrupts, the RISC-V PLIC spec in plic_map_intr()
250 * active; the PLIC may either queue them or ignore them. In the first in plic_map_intr()
256 * and the T-HEAD C900 PLIC." in plic_map_intr()
283 device_set_desc(dev, "RISC-V PLIC"); in plic_probe()
351 * This is tricky for a few reasons. The PLIC divides the interrupt in plic_attach()
355 * The tricky part is that the PLIC spec imposes no restrictions on how in plic_attach()
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/freebsd/sys/contrib/device-tree/src/riscv/allwinner/
H A Dsun20i-d1s.dtsi56 interrupt-parent = <&plic>;
66 plic: interrupt-controller@10000000 {
67 compatible = "allwinner,sun20i-d1-plic",
68 "thead,c900-plic";
64 plic: interrupt-controller@10000000 { global() label
/freebsd/sys/contrib/device-tree/src/riscv/renesas/
H A Dr9a07g043f.dtsi51 interrupt-parent = <&plic>;
53 plic: interrupt-controller@12c00000 {
54 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
47 plic: interrupt-controller@12c00000 { global() label
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7100.dtsi146 interrupt-parent = <&plic>;
170 plic: interrupt-controller@c000000 {
171 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
125 plic: interrupt-controller@c000000 { global() label
H A Djh7110.dtsi349 interrupt-parent = <&plic>;
375 plic: interrupt-controller@c000000 {
376 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
300 plic: interrupt-controller@c000000 { global() label
/freebsd/sys/contrib/device-tree/src/riscv/thead/
H A Dth1520.dtsi158 interrupt-parent = <&plic>;
164 plic: interrupt-controller@ffd8000000 {
165 compatible = "thead,th1520-plic", "thead,c900-plic";
144 plic: interrupt-controller@ffd8000000 { global() label
/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dmicrochip,mpfs-can.yaml43 interrupt-parent = <&plic>;
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dmicrochip,mpfs-musb.yaml53 interrupt-parent = <&plic>;
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmicrochip,mpfs-spi.yaml55 interrupt-parent = <&plic>;
H A Dspi-sifive.yaml78 interrupt-parent = <&plic>;
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dmicrochip,corei2c.yaml52 interrupt-parent = <&plic>;
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-sifive.txt30 interrupt-parent = <&plic>;
H A Dpwm-sifive.yaml69 interrupt-parent = <&plic>;
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dsifive,gpio.yaml82 interrupt-parent = <&plic>;
H A Dmicrochip,mpfs-gpio.yaml83 interrupt-parent = <&plic>;
/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";

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