Lines Matching full:plic

5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12   Platform-Level Interrupt Controller (PLIC) high-level specification in
13   the RISC-V Privileged Architecture specification. The PLIC connects all
26   with priority below this threshold will not cause the PLIC to raise its
29   The PLIC supports both edge-triggered and level-triggered interrupts. For
30   edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31   seen while an interrupt handler is active; the PLIC may either queue them or
36   RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
43   The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44   T-HEAD PLIC implementation requires setting a delegation bit to allow access
45   from S-mode. So add thead,c900-plic to distinguish them.
56               - renesas,r9a07g043-plic
60               - canaan,k210-plic
61               - sifive,fu540-c000-plic
62               - starfive,jh7100-plic
63               - starfive,jh7110-plic
64           - const: sifive,plic-1.0.0
67               - allwinner,sun20i-d1-plic
68               - sophgo,cv1800b-plic
69               - sophgo,cv1812h-plic
70               - sophgo,sg2042-plic
71               - thead,th1520-plic
72           - const: thead,c900-plic
74           - const: sifive,plic-1.0.0
93       Specifies which contexts are connected to the PLIC, with "-1" specifying
124               - thead,c900-plic
140             const: renesas,r9a07g043-plic
162     plic: interrupt-controller@c000000 {
165       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";