Lines Matching full:plic

1 SiFive Platform-Level Interrupt Controller (PLIC)
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
6 specification.  The PLIC connects all external interrupts in the system to all
18 with priority below this threshold will not cause the PLIC to raise its
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
37 - interrupts-extended : Specifies which contexts are connected to the PLIC,
45 	plic: interrupt-controller@c000000 {
48 		compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";